Searched refs:SynchronizeDRRDisplaysForUCLKPStateChangeFinal (Results 1 - 8 of 8) sorted by relevance

/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddisplay_mode_vba_util_32.h592 bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
683 bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
H A Ddisplay_mode_vba_util_32.c2922 bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
3044 SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
3247 bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
3260 !(SynchronizeDRRDisplaysForUCLKPStateChangeFinal && DRRDisplay)) {
4498 v->VActive[i] == v->VActive[j]) || (v->SynchronizeDRRDisplaysForUCLKPStateChangeFinal &&
2921 dml32_UseMinimumDCFCLK( enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange[], bool DRRDisplay[], bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal, unsigned int MaxInterDCNTileRepeaters, unsigned int MaxPrefetchMode, double DRAMClockChangeLatencyFinal, double FCLKChangeLatency, double SREnterPlusExitTime, unsigned int ReturnBusWidth, unsigned int RoundTripPingLatencyCycles, unsigned int ReorderingBytes, unsigned int PixelChunkSizeInKByte, unsigned int MetaChunkSize, bool GPUVMEnable, unsigned int GPUVMMaxPageTableLevels, bool HostVMEnable, unsigned int NumberOfActiveSurfaces, double HostVMMinPageSize, unsigned int HostVMMaxNonCachedPageTableLevels, bool DynamicMetadataVMEnabled, bool ImmediateFlipRequirement, bool ProgressiveToInterlaceUnitInOPP, double MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation, double PercentOfIdealSDPPortBWReceivedAfterUrgLatency, unsigned int VTotal[], unsigned int VActive[], unsigned int DynamicMetadataTransmittedBytes[], unsigned int DynamicMetadataLinesBeforeActiveRequired[], bool Interlace[], double RequiredDPPCLKPerSurface[][2][DC__NUM_DPP__MAX], double RequiredDISPCLK[][2], double UrgLatency[], unsigned int NoOfDPP[][2][DC__NUM_DPP__MAX], double ProjectedDCFClkDeepSleep[][2], double MaximumVStartup[][2][DC__NUM_DPP__MAX], unsigned int TotalNumberOfActiveDPP[][2], unsigned int TotalNumberOfDCCActiveDPP[][2], unsigned int dpte_group_bytes[], double PrefetchLinesY[][2][DC__NUM_DPP__MAX], double PrefetchLinesC[][2][DC__NUM_DPP__MAX], unsigned int swath_width_luma_ub_all_states[][2][DC__NUM_DPP__MAX], unsigned int swath_width_chroma_ub_all_states[][2][DC__NUM_DPP__MAX], unsigned int BytePerPixelY[], unsigned int BytePerPixelC[], unsigned int HTotal[], double PixelClock[], double PDEAndMetaPTEBytesPerFrame[][2][DC__NUM_DPP__MAX], double DPTEBytesPerRow[][2][DC__NUM_DPP__MAX], double MetaRowBytes[][2][DC__NUM_DPP__MAX], bool DynamicMetadataEnable[], double ReadBandwidthLuma[], double ReadBandwidthChroma[], double DCFCLKPerState[], double DCFCLKState[][2]) argument
3246 dml32_CalculateTWait( unsigned int PrefetchMode, enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange, bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal, bool DRRDisplay, double DRAMClockChangeLatency, double FCLKChangeLatency, double UrgentLatency, double SREnterPlusExitTime) argument
H A Ddisplay_mode_vba_32.c755 mode_lib->vba.SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
3057 mode_lib->vba.SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
3261 mode_lib->vba.SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
/linux-master/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddml2_policy.c300 policy->SynchronizeDRRDisplaysForUCLKPStateChangeFinal = true;
H A Ddisplay_mode_core_structs.h655 dml_bool_t SynchronizeDRRDisplaysForUCLKPStateChangeFinal; member in struct:dml_mode_eval_policy_st
1215 dml_bool_t SynchronizeDRRDisplaysForUCLKPStateChangeFinal; member in struct:UseMinimumDCFCLK_params_st
1280 dml_bool_t SynchronizeDRRDisplaysForUCLKPStateChangeFinal; member in struct:CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params_st
H A Ddisplay_mode_util.c341 dml_print("DML: Policy: SynchronizeDRRDisplaysForUCLKPStateChangeFinal = 0x%x\n", policy->SynchronizeDRRDisplaysForUCLKPStateChangeFinal);
H A Ddisplay_mode_core.c277 dml_bool_t SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
1740 dml_bool_t SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
1751 !(UseMALLForPStateChange == dml_use_mall_pstate_change_phantom_pipe) && !(SynchronizeDRRDisplaysForUCLKPStateChangeFinal && DRRDisplay)) {
2980 (p->SynchronizeDRRDisplaysForUCLKPStateChangeFinal && (p->DRRDisplay[i] || p->DRRDisplay[j]))) {
2994 s->FCLKChangeSupportNumber = ((p->SynchronizeDRRDisplaysForUCLKPStateChangeFinal && p->DRRDisplay[k]) ? 2 : 1);
3025 s->DRAMClockChangeSupportNumber = (p->SynchronizeDRRDisplaysForUCLKPStateChangeFinal && p->DRRDisplay[k]) ? 2 : 1;
4631 p->SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
6352 mode_lib->ms.policy.SynchronizeDRRDisplaysForUCLKPStateChangeFinal,
6653 CalculateWatermarks_params->SynchronizeDRRDisplaysForUCLKPStateChangeFinal = mode_lib->ms.policy.SynchronizeDRRDisplaysForUCLKPStateChangeFinal;
1735 CalculateTWait( dml_uint_t PrefetchMode, enum dml_use_mall_for_pstate_change_mode UseMALLForPStateChange, dml_bool_t SynchronizeDRRDisplaysForUCLKPStateChangeFinal, dml_bool_t DRRDisplay, dml_float_t DRAMClockChangeLatency, dml_float_t FCLKChangeLatency, dml_float_t UrgentLatency, dml_float_t SREnterPlusExitTime) argument
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_mode_vba.h447 bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal; member in struct:vba_vars_st

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