Searched refs:SF (Results 1 - 25 of 54) sorted by relevance

123

/linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn32/
H A Ddcn32_optc.h32 SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
33 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
34 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
35 SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
36 SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
37 SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
38 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_START_X, mask_sh),\
39 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_END_X, mask_sh),\
40 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
41 SF(OTG0_OTG_GLOBAL_CONTROL
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn35/
H A Ddcn35_optc.h34 SF(OTG0_OTG_CRC_CNTL, OTG_CRC_WINDOW_DB_EN, mask_sh),\
35 SF(OTG0_OTG_CRC1_DATA_RG, CRC1_R_CR, mask_sh),\
36 SF(OTG0_OTG_CRC1_DATA_RG, CRC1_G_Y, mask_sh),\
37 SF(OTG0_OTG_CRC1_DATA_B, CRC1_B_CB, mask_sh),\
38 SF(OTG0_OTG_CRC2_DATA_RG, CRC2_R_CR, mask_sh),\
39 SF(OTG0_OTG_CRC2_DATA_RG, CRC2_G_Y, mask_sh),\
40 SF(OTG0_OTG_CRC2_DATA_B, CRC2_B_CB, mask_sh),\
41 SF(OTG0_OTG_CRC3_DATA_RG, CRC3_R_CR, mask_sh),\
42 SF(OTG0_OTG_CRC3_DATA_RG, CRC3_G_Y, mask_sh),\
43 SF(OTG0_OTG_CRC3_DATA_
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn314/
H A Ddcn314_optc.h104 SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
105 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
106 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
107 SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
108 SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
109 SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
110 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_START_X, mask_sh),\
111 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_END_X, mask_sh),\
112 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
113 SF(OTG0_OTG_GLOBAL_CONTROL
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn30/
H A Ddcn30_optc.h117 SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
118 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
119 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
120 SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
121 SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
122 SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
123 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_START_X, mask_sh),\
124 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_END_X, mask_sh),\
125 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
126 SF(OTG0_OTG_GLOBAL_CONTROL
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn201/
H A Ddcn201_optc.h46 SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_X, mask_sh),\
47 SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_Y, mask_sh),\
48 SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
49 SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\
50 SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mask_sh),\
51 SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\
52 SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
53 SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\
54 SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\
55 SF(OTG0_OTG_VUPDATE_KEEPOU
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_mmhubbub.h84 SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\
85 SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\
86 SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\
87 SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\
88 SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\
89 SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\
90 SF(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\
91 SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_INT_STATUS, mask_sh),\
92 SF(MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS, mask_sh),\
93 SF(MCIF_WB_BUFMGR_STATU
[all...]
H A Ddcn32_mpc.h180 SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
181 SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\
182 SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\
183 SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\
184 SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\
185 SF(MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL, MPCC_MOVABLE_CM_LOCATION_CNTL, mask_sh),\
186 SF(MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL, MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT, mask_sh),\
187 SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\
188 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\
189 SF(MPC_OUT0_CSC_C11_C12_
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_mmhubbub.h136 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\
137 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\
138 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\
139 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\
140 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\
141 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\
142 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\
143 SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_VCE_INT_STATUS, mask_sh),\
144 SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_INT_STATUS, mask_sh),\
145 SF(MCIF_WB0_MCIF_WB_BUFMGR_STATU
[all...]
H A Ddcn30_mpc.h429 SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
430 SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\
431 SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\
432 SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\
433 SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\
434 SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\
435 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\
436 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\
437 SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\
438 SF(MPCC0_MPCC_MEM_PWR_CTR
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn31/
H A Ddcn31_optc.h105 SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
106 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
107 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
108 SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
109 SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
110 SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
111 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_START_X, mask_sh),\
112 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_END_X, mask_sh),\
113 SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
114 SF(OTG0_OTG_GLOBAL_CONTROL
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn20/
H A Ddcn20_optc.h50 SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_X, mask_sh),\
51 SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_Y, mask_sh),\
52 SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
53 SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\
54 SF(OTG0_OTG_GLOBAL_CONTROL2, DIG_UPDATE_LOCATION, mask_sh),\
55 SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mask_sh),\
56 SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\
57 SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
58 SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\
59 SF(OTG0_OTG_GSL_WINDOW_
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_dwb.h47 #define SF(reg_name, field_name, post_fix)\ macro
85 SF(CNV0_WB_ENABLE, WB_ENABLE, mask_sh),\
86 SF(CNV0_WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\
87 SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\
88 SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\
89 SF(CNV0_WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\
90 SF(CNV0_WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\
91 SF(CNV0_CNV_MODE, CNV_WINDOW_CROP_EN, mask_sh),\
92 SF(CNV0_CNV_MODE, CNV_STEREO_TYPE, mask_sh),\
93 SF(CNV0_CNV_MOD
[all...]
H A Ddcn10_mpc.h64 SF(MPCC0_MPCC_TOP_SEL, MPCC_TOP_SEL, mask_sh),\
65 SF(MPCC0_MPCC_BOT_SEL, MPCC_BOT_SEL, mask_sh),\
66 SF(MPCC0_MPCC_CONTROL, MPCC_MODE, mask_sh),\
67 SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_BLND_MODE, mask_sh),\
68 SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_MULTIPLIED_MODE, mask_sh),\
69 SF(MPCC0_MPCC_CONTROL, MPCC_BLND_ACTIVE_OVERLAP_ONLY, mask_sh),\
70 SF(MPCC0_MPCC_CONTROL, MPCC_GLOBAL_ALPHA, mask_sh),\
71 SF(MPCC0_MPCC_CONTROL, MPCC_GLOBAL_GAIN, mask_sh),\
72 SF(MPCC0_MPCC_STATUS, MPCC_IDLE, mask_sh),\
73 SF(MPCC0_MPCC_STATU
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_audio.h44 #define SF(reg_name, field_name, post_fix)\ macro
49 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\
50 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
51 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO2_USE_512FBR_DTO, mask_sh),\
52 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_USE_512FBR_DTO, mask_sh),\
53 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO1_USE_512FBR_DTO, mask_sh),\
54 SF(DCCG_AUDIO_DTO0_MODULE, DCCG_AUDIO_DTO0_MODULE, mask_sh),\
55 SF(DCCG_AUDIO_DTO0_PHASE, DCCG_AUDIO_DTO0_PHASE, mask_sh),\
56 SF(DCCG_AUDIO_DTO1_MODULE, DCCG_AUDIO_DTO1_MODULE, mask_sh),\
57 SF(DCCG_AUDIO_DTO1_PHAS
[all...]
H A Ddce_mem_input.h246 SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, mask_sh),\
247 SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED, mask_sh)
274 SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, mask_sh),\
275 SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED, mask_sh)
321 SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\
322 SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\
323 SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\
324 SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\
325 SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh)
329 SF(DCP0_GRPH_SECONDARY_SURFACE_ADDRES
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_mmhubbub.h91 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\
92 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\
93 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\
94 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\
95 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\
96 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\
97 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_P_VMID, mask_sh),\
98 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\
99 SF(MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R, MCIF_WB_BUFMGR_CUR_LINE_R, mask_sh),\
100 SF(MCIF_WB0_MCIF_WB_BUFMGR_STATU
[all...]
H A Ddcn20_vmid.h41 SF(DCN_VM_CONTEXT0_CNTL, VM_CONTEXT0_PAGE_TABLE_DEPTH, mask_sh),\
42 SF(DCN_VM_CONTEXT0_CNTL, VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE, mask_sh),\
43 SF(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\
44 SF(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\
45 SF(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4, mask_sh),\
46 SF(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32, mask_sh),\
47 SF(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4, mask_sh),\
48 SF(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32, mask_sh)
H A Ddcn20_mpc.h138 SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
139 SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\
140 SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\
141 SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\
142 SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\
143 SF(MPC_OCSC_TEST_DEBUG_INDEX, MPC_OCSC_TEST_DEBUG_INDEX, mask_sh),\
144 SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\
145 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\
146 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\
147 SF(MPCC0_MPCC_STATU
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn10/
H A Ddcn10_optc.h204 SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
205 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
206 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
207 SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
208 SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DATA_EN, mask_sh),\
209 SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DE_MODE, mask_sh),\
210 SF(OTG0_OTG_BLANK_CONTROL, OTG_CURRENT_BLANK_STATE, mask_sh),\
211 SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
212 SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
213 SF(OTG0_OTG_GLOBAL_CONTROL
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dcn35/
H A Ddcn35_mmhubbub.h39 SF(MMHUBBUB_CLOCK_CNTL, MMHUBBUB_TEST_CLK_SEL, mask_sh), \
40 SF(MMHUBBUB_CLOCK_CNTL, DISPCLK_R_MMHUBBUB_GATE_DIS, mask_sh), \
41 SF(MMHUBBUB_CLOCK_CNTL, DISPCLK_G_WBIF0_GATE_DIS, mask_sh), \
42 SF(MMHUBBUB_CLOCK_CNTL, SOCCLK_G_WBIF0_GATE_DIS, mask_sh), \
43 SF(MMHUBBUB_CLOCK_CNTL, MMHUBBUB_FGCG_REP_DIS, mask_sh)
/linux-master/drivers/gpu/drm/amd/display/dc/dcn201/
H A Ddcn201_mpc.h44 SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL, mask_sh),\
45 SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL_DISABLE, mask_sh),\
46 SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_MODE, mask_sh),\
47 SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_COUNT0, mask_sh),\
48 SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_COUNT1, mask_sh)
/linux-master/fs/reiserfs/
H A Dprocfs.c50 #define SF( x ) ( r -> x ) macro
51 #define SFP( x ) SF( s_proc_info_data.x )
102 SF(s_mount_state) == REISERFS_VALID_FS ?
118 SF(s_disk_reads), SF(s_disk_writes), SF(s_fix_nodes),
119 SF(s_do_balance), SF(s_unneeded_left_neighbor),
120 SF(s_good_search_by_key_reada), SF(s_bmap
[all...]
/linux-master/scripts/selinux/
H A Dinstall_policy.sh9 SF=`which setfiles`
77 $SF -F file_contexts /
82 $SF -F file_contexts $mounts
/linux-master/drivers/gpu/drm/nouveau/dispnv50/
H A Dcrcc57d.c29 crc_args |= NVDEF(NVC57D, HEAD_SET_CRC_CONTROL, PRIMARY_CRC, SF);
/linux-master/drivers/gpu/drm/amd/display/dc/gpio/dcn21/
H A Dhw_factory_dcn21.c67 #define SF(reg_name, field_name, post_fix)\ macro

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