Searched refs:SDMA0_CNTL (Results 1 - 11 of 11) sorted by relevance

/linux-master/drivers/gpu/drm/radeon/
H A Dcik_reg.h204 #define SDMA0_CNTL 0xD010 macro
H A Dcik_sdma.c313 value = RREG32(SDMA0_CNTL + reg_offset);
318 WREG32(SDMA0_CNTL + reg_offset, value);
H A Dcik.c6863 tmp = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
6864 WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, tmp);
6865 tmp = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
6866 WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, tmp);
7048 dma_cntl = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
7049 dma_cntl1 = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
7219 WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, dma_cntl);
7220 WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, dma_cntl1);
H A Dcikd.h1960 #define SDMA0_CNTL 0xD010 macro
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v3_0.c578 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
580 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
589 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
591 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
1335 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1340 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1351 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1356 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
H A Dsdma_v2_4.c999 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1004 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1015 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1020 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
H A Dsdma_v5_0.c612 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
767 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
770 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
1535 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
H A Dsdma_v5_2.c430 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
571 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
574 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
1387 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
H A Dcik_sdma.c371 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
380 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
H A Dsdma_v4_0.c965 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
1368 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
2009 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
H A Dsdma_v6_0.c378 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
1414 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,

Completed in 217 milliseconds