Searched refs:ResultReg (Results 1 - 17 of 17) sorted by last modified time

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastISel.cpp89 unsigned &ResultReg, unsigned Alignment = 1);
98 unsigned &ResultReg);
319 MachineMemOperand *MMO, unsigned &ResultReg,
470 ResultReg = createResultReg(RC);
472 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg);
707 unsigned &ResultReg) {
713 ResultReg = RR;
1330 unsigned ResultReg = 0; local
1331 if (!X86FastEmitLoad(VT, AM, createMachineMemOperandFor(LI), ResultReg,
1335 updateValueMap(I, ResultReg);
318 X86FastEmitLoad(MVT VT, X86AddressMode &AM, MachineMemOperand *MMO, unsigned &ResultReg, unsigned Alignment) argument
705 X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT, unsigned &ResultReg) argument
1435 unsigned ResultReg = 0; local
1525 unsigned ResultReg = getRegForValue(I->getOperand(0)); local
1584 unsigned ResultReg = getRegForValue(I->getOperand(0)); local
1842 unsigned ResultReg = createResultReg(RC); local
1985 unsigned ResultReg = 0; local
2136 unsigned ResultReg = fastEmitInst_rri(Opc, RC, RHSReg, RHSIsKill, local
2201 unsigned ResultReg; local
2354 unsigned ResultReg = local
2381 unsigned ResultReg = createResultReg(RC); local
2454 unsigned ResultReg = local
2489 unsigned ResultReg = createResultReg(RC); local
2552 unsigned ResultReg = fastEmitInst_extractsubreg(MVT::i8, local
2625 unsigned ResultReg = 0; local
2846 unsigned ResultReg = createResultReg(RC); local
2911 unsigned ResultReg = 0; local
3048 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); local
3146 unsigned ResultReg = createResultReg(RC); local
3271 unsigned ResultReg; local
3552 unsigned ResultReg = FuncInfo.CreateRegs(CLI.RetTy); local
3704 unsigned ResultReg = createResultReg(&X86::GR64RegClass); local
3790 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy)); local
3827 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); local
3886 unsigned ResultReg = createResultReg(RC); local
3919 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); local
3983 unsigned ResultReg = createResultReg(RC); local
[all...]
H A DX86InstructionSelector.cpp1028 Register ResultReg = I.getOperand(0).getReg(); local
1030 ResultReg,
1031 *getRegClass(LLT::scalar(8), *RBI.getRegBank(ResultReg, MRI, TRI)), MRI);
1045 TII.get(SETFOpc[2]), ResultReg)
1072 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::SETCCr), ResultReg).addImm(CC);
H A DX86FlagsCopyLowering.cpp1079 Register ResultReg = MRI->createVirtualRegister(&SetBRC); local
1080 BuildMI(MBB, SetPos, SetLoc, TII->get(Sub), ResultReg)
1083 return RewriteToReg(ResultReg);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp628 unsigned ResultReg = local
631 if (!ResultReg)
635 updateValueMap(I, ResultReg);
662 unsigned ResultReg = fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, local
664 if (!ResultReg)
668 updateValueMap(I, ResultReg);
678 unsigned ResultReg = fastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), local
680 if (!ResultReg)
686 updateValueMap(I, ResultReg);
957 CLI.ResultReg
1485 unsigned ResultReg = getRegForValue(II->getArgOperand(0)); local
1530 unsigned ResultReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), local
1565 unsigned ResultReg = 0; local
1733 unsigned ResultReg = fastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(), ISD::FNEG, local
1786 unsigned ResultReg; local
2010 unsigned ResultReg = fastEmit_ri(VT, VT, Opcode, Op0, Op0IsKill, Imm); local
2057 unsigned ResultReg = createResultReg(RC); local
2069 unsigned ResultReg = createResultReg(RC); local
2091 unsigned ResultReg = createResultReg(RC); local
2116 unsigned ResultReg = createResultReg(RC); local
2142 unsigned ResultReg = createResultReg(RC); local
2165 unsigned ResultReg = createResultReg(RC); local
2189 unsigned ResultReg = createResultReg(RC); local
2209 unsigned ResultReg = createResultReg(RC); local
2231 unsigned ResultReg = createResultReg(RC); local
2247 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp590 unsigned ResultReg = createResultReg(MRI.getRegClass(Reg)); local
592 ResultReg)
594 return ResultReg;
602 unsigned ResultReg = local
607 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
609 return ResultReg;
621 unsigned ResultReg = local
626 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
628 return ResultReg;
712 unsigned ResultReg local
764 unsigned ResultReg; local
936 unsigned ResultReg = createResultReg(RC); local
1052 unsigned ResultReg = createResultReg(&WebAssembly::I32RegClass); local
1113 unsigned ResultReg = createResultReg(&WebAssembly::I32RegClass); local
1203 unsigned ResultReg = createResultReg(RC); local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp165 bool PPCEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
435 unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass); local
437 ResultReg).addFrameIndex(Addr.Base.FI).addImm(0);
438 Addr.Base.Reg = ResultReg;
454 bool PPCFastISel::PPCEmitLoad(MVT VT, Register &ResultReg, Address &Addr, argument
461 // If ResultReg is given, it determines the register class of the load.
469 (ResultReg ? MRI.getRegClass(ResultReg) :
525 if (ResultReg == 0)
526 ResultReg
615 Register ResultReg = 0; local
1054 Register ResultReg = 0; local
1179 Register ResultReg = 0; local
1300 unsigned ResultReg = createResultReg(RC ? RC : &PPC::G8RCRegClass); local
1518 unsigned ResultReg = 0; local
1926 unsigned ResultReg = createResultReg(RC); local
2116 unsigned ResultReg = createResultReg(RC); local
2188 unsigned ResultReg = createResultReg(RC); local
2276 unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass); local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp181 bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
329 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); local
330 if (!ResultReg)
333 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg);
334 return ResultReg;
345 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); local
347 ResultReg)
350 return ResultReg;
366 unsigned ResultReg = createResultReg(RC); local
370 emitInst(Opc, ResultReg)
638 emitCmp(unsigned ResultReg, const CmpInst *CI) argument
757 emitLoad(MVT VT, unsigned &ResultReg, Address &Addr, unsigned Alignment) argument
870 unsigned ResultReg; local
907 unsigned ResultReg; local
988 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); local
1061 unsigned ResultReg = createResultReg(RC); local
1300 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT)); local
1472 unsigned ResultReg = createResultReg(Allocation[ArgNo].RC); local
1824 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); local
1949 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); local
1968 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); local
2136 unsigned ResultReg = createResultReg(RC); local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp690 auto ResultReg = MIB->getOperand(0).getReg(); local
698 .addDef(ResultReg)
H A DARMFastISel.cpp195 bool ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
304 Register ResultReg = createResultReg(RC); local
312 ResultReg).addReg(Op0, Op0IsKill * RegState::Kill));
317 TII.get(TargetOpcode::COPY), ResultReg)
320 return ResultReg;
327 unsigned ResultReg = createResultReg(RC); local
337 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
345 TII.get(TargetOpcode::COPY), ResultReg)
348 return ResultReg;
355 unsigned ResultReg local
380 unsigned ResultReg = createResultReg(RC); local
499 unsigned ResultReg = 0; local
676 unsigned ResultReg = createResultReg(RC); local
851 unsigned ResultReg = createResultReg(RC); local
916 ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr, unsigned Alignment, bool isZExt, bool allocReg) argument
1575 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT)); local
1602 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32)); local
1668 unsigned ResultReg = createResultReg(RC); local
1779 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass); local
1828 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy)); local
2055 Register ResultReg = createResultReg(DstRC); local
2076 Register ResultReg = createResultReg(DstRC); local
2469 Register ResultReg; local
2703 unsigned ResultReg; local
2761 unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt); local
2803 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass); local
3067 unsigned ResultReg = createResultReg(RC); local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.cpp1092 Register ResultReg = IsCopy ? local
1103 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_LSHRREV_B32_e64), ResultReg)
1107 if (auto MIB = TII->getAddNoCarry(*MBB, MI, DL, ResultReg, *RS)) {
1159 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::COPY), ResultReg)
1185 FIOp.ChangeToRegister(ResultReg, false, false, true);
H A DSIInstrInfo.cpp5121 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5135 MRI.replaceRegWith(OldDstReg, ResultReg);
5138 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
5155 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5164 BuildMI(MBB, MII, DL, get(AMDGPU::V_MAX_I32_e64), ResultReg)
5168 MRI.replaceRegWith(Dest.getReg(), ResultReg);
5169 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
5544 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5555 BuildMI(MBB, MII, DL, InstDesc, ResultReg).add(SrcRegSub1).addReg(MidReg);
5557 MRI.replaceRegWith(Dest.getReg(), ResultReg);
[all...]
H A DSIISelLowering.cpp3178 unsigned ResultReg,
3198 .addReg(ResultReg)
3170 emitLoadM0FromVGPRLoop( const SIInstrInfo *TII, MachineRegisterInfo &MRI, MachineBasicBlock &OrigBB, MachineBasicBlock &LoopBB, const DebugLoc &DL, const MachineOperand &IdxReg, unsigned InitReg, unsigned ResultReg, unsigned PhiReg, unsigned InitSaveExecReg, int Offset, bool UseGPRIdxMode, bool IsIndirectSrc) argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp4178 Register ResultReg = Root.getOperand(0).getReg(); local
4195 if (Register::isVirtualRegister(ResultReg))
4196 MRI.constrainRegClass(ResultReg, RC);
4206 MIB = BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc), ResultReg)
4211 MIB = BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc), ResultReg)
4217 MIB = BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc), ResultReg)
4329 Register ResultReg = Root.getOperand(0).getReg(); local
4335 if (Register::isVirtualRegister(ResultReg))
4336 MRI.constrainRegClass(ResultReg, RC);
4345 BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc), ResultReg)
[all...]
H A DAArch64FastISel.cpp368 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass); local
370 ResultReg)
374 return ResultReg;
391 unsigned ResultReg = createResultReg(RC); local
393 ResultReg).addReg(ZeroReg, getKillRegState(true));
394 return ResultReg;
427 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); local
429 TII.get(TargetOpcode::COPY), ResultReg)
432 return ResultReg;
447 unsigned ResultReg local
471 unsigned ResultReg; local
1056 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass); local
1067 unsigned ResultReg = 0; local
1105 unsigned ResultReg; local
1212 unsigned ResultReg = 0; local
1337 unsigned ResultReg; local
1382 unsigned ResultReg; local
1424 unsigned ResultReg; local
1469 unsigned ResultReg; local
1567 unsigned ResultReg; local
1629 unsigned ResultReg = 0; local
1727 unsigned ResultReg = local
1770 unsigned ResultReg = local
1896 unsigned ResultReg = createResultReg(RC); local
1930 unsigned ResultReg; local
1956 unsigned ResultReg; local
2025 unsigned ResultReg = local
2577 unsigned ResultReg = 0; local
2703 unsigned ResultReg = fastEmitInst_rr(Opc, &AArch64::GPR32RegClass, Src1Reg, local
2833 unsigned ResultReg = fastEmitInst_rri(Opc, RC, Src1Reg, Src1IsKill, Src2Reg, local
2848 unsigned ResultReg = createResultReg(&AArch64::FPR64RegClass); local
2864 unsigned ResultReg = createResultReg(&AArch64::FPR32RegClass); local
2897 unsigned ResultReg = createResultReg( local
2945 unsigned ResultReg = fastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg, local
3053 unsigned ResultReg = createResultReg(RC); local
3178 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT)); local
3367 unsigned ResultReg = emitLoad(VT, VT, Src); local
3512 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass); local
3646 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); local
3677 unsigned ResultReg = fastEmit_r(VT, VT, ISD::FSQRT, Op0Reg, Op0IsKill); local
3979 unsigned ResultReg; local
4022 unsigned ResultReg = emitAnd_ri(MVT::i32, SrcReg, /*TODO:IsKill=*/false, 1); local
4105 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg, local
4133 unsigned ResultReg = createResultReg(RC); local
4212 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg, local
4240 unsigned ResultReg = createResultReg(RC); local
4333 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg, local
4361 unsigned ResultReg = createResultReg(RC); local
4610 unsigned ResultReg = createResultReg(&AArch64::GPR64RegClass); local
4631 unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt); local
4678 unsigned ResultReg = fastEmitInst_rrr(MSubOpc, RC, QuotReg, /*IsKill=*/true, local
4730 unsigned ResultReg = local
4749 unsigned ResultReg = emitMul_rr(VT, Src0Reg, Src0IsKill, Src1Reg, Src1IsKill); local
4767 unsigned ResultReg = 0; local
4826 unsigned ResultReg = 0; local
4879 unsigned ResultReg = fastEmitInst_r(Opc, RC, Op0Reg, Op0IsKill); local
4946 unsigned ResultReg = emitASR_ri(VT, VT, Src0Reg, Src0IsKill, Lg2); local
4980 unsigned ResultReg; local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp669 for (unsigned ResultReg : ResultRegs)
670 MIB.addDef(ResultReg);
H A DLegalizerHelper.cpp1199 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src1).getReg(0); local
1214 MIRBuilder.buildOr(NextResult, ResultReg, Shl);
1215 ResultReg = NextResult;
1219 MIRBuilder.buildTrunc(DstReg, ResultReg);
1221 MIRBuilder.buildIntToPtr(DstReg, ResultReg);
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DFastISel.h91 unsigned ResultReg = 0; member in struct:llvm::FastISel::CallLoweringInfo

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