Searched refs:REG_ADDR (Results 1 - 15 of 15) sorted by relevance

/linux-master/drivers/net/ethernet/apm/xgene/
H A Dxgene_enet_sgmac.h13 #define REG_ADDR(src) ((src) & GENMASK(4, 0)) macro
H A Dxgene_enet_sgmac.c119 addr = PHY_ADDR(phy_id) | REG_ADDR(reg);
140 addr = PHY_ADDR(phy_id) | REG_ADDR(reg);
/linux-master/include/linux/mfd/
H A Didt82p33_reg.h10 #define REG_ADDR(page, offset) (((page) << 0x7) | ((offset) & 0x7f)) macro
45 #define OUT_MUX_CNFG(outn) REG_ADDR(0x6, (0xC * (outn)))
/linux-master/drivers/net/ethernet/apm/xgene-v2/
H A Dmdio.c19 SET_REG_BITS(&val, REG_ADDR, reg);
43 SET_REG_BITS(&val, REG_ADDR, reg);
/linux-master/drivers/net/ethernet/chelsio/cxgb/
H A Dmy3126.c35 #define OFFSET(REG_ADDR) (REG_ADDR << 2)
H A Dpm3393.c39 #define OFFSET(REG_ADDR) ((REG_ADDR) << 2)
/linux-master/drivers/hwmon/
H A Dultra45_env.c37 #define REG_ADDR 0x41UL macro
40 /* Registers accessed indirectly via REG_DATA/REG_ADDR */
74 writeb(ireg, p->regs + REG_ADDR);
84 writeb(ireg, p->regs + REG_ADDR);
/linux-master/drivers/net/mdio/
H A Dmdio-xgene.c86 data = SET_VAL(PHY_ADDR, phy_id) | SET_VAL(REG_ADDR, reg);
112 val = SET_VAL(PHY_ADDR, phy_id) | SET_VAL(REG_ADDR, reg);
/linux-master/drivers/net/ethernet/qlogic/qed/
H A Dqed.h957 #define REG_ADDR(cdev, offset) ((void __iomem *)((u8 __iomem *)\ macro
961 #define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset))
962 #define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset))
963 #define REG_WR16(cdev, offset, val) writew((u16)val, REG_ADDR(cdev, offset))
H A Dqed_hw.c264 reg_addr = (u32 __iomem *)REG_ADDR(p_hwfn, hw_offset);
/linux-master/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x.h169 #define REG_ADDR(bp, offset) ((bp->regview) + (offset)) macro
171 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
172 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
173 #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset))
176 writel_relaxed((u32)val, REG_ADDR(bp, offset))
179 writew_relaxed((u16)val, REG_ADDR(bp, offset))
181 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
182 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
183 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
H A Dbnx2x_vfpf.c144 REG_ADDR(bp, PXP_VF_ADDR_CSDM_GLOBAL_START);
/linux-master/drivers/gpu/drm/panel/
H A Dpanel-raspberrypi-touchscreen.c61 enum REG_ADDR { enum
/linux-master/drivers/spi/
H A Dspi-meson-spifc.c23 #define REG_ADDR 0x04 macro
/linux-master/drivers/ptp/
H A Dptp_idt82p33.c1327 err = idt82p33_write(idt82p33, REG_ADDR(page, loaddr),

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