Searched refs:REGS_SOUTH_SHARED (Results 1 - 2 of 2) sorted by relevance

/haiku/headers/private/graphics/intel_extreme/
H A Dintel_extreme.h148 #define REGS_SOUTH_SHARED (4 << REGISTER_BLOCK_SHIFT) macro
1273 #define PCH_DREF_CONTROL (0x6200 | REGS_SOUTH_SHARED)
1296 #define PCH_RAWCLK_FREQ (0x6204 | REGS_SOUTH_SHARED)
1301 #define INTEL_DISPLAY_A_PLL (0x6014 | REGS_SOUTH_SHARED)
1302 #define INTEL_DISPLAY_B_PLL (0x6018 | REGS_SOUTH_SHARED)
1303 #define INTEL_DISPLAY_A_PLL_MD (0x601C | REGS_SOUTH_SHARED)
1304 #define INTEL_DISPLAY_B_PLL_MD (0x6020 | REGS_SOUTH_SHARED)
1305 #define CHV_DISPLAY_C_PLL (0x6030 | REGS_SOUTH_SHARED)
1306 #define CHV_DISPLAY_B_PLL_MD (0x603C | REGS_SOUTH_SHARED)
1308 #define INTEL_DISPLAY_A_PLL_DIVISOR_0 (0x6040 | REGS_SOUTH_SHARED)
[all...]
/haiku/src/add-ons/kernel/drivers/graphics/intel_extreme/
H A Dintel_extreme.cpp680 blocks[REGISTER_BLOCK(REGS_SOUTH_SHARED)]
692 blocks[REGISTER_BLOCK(REGS_SOUTH_SHARED)]
701 blocks[REGISTER_BLOCK(REGS_SOUTH_SHARED)] += VLV_DISPLAY_BASE;
711 TRACE("REGS_SOUTH_SHARED: 0x%" B_PRIx32 "\n",
712 blocks[REGISTER_BLOCK(REGS_SOUTH_SHARED)]);

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