Searched refs:REGS_NORTH_PIPE_AND_PORT (Results 1 - 2 of 2) sorted by relevance

/haiku/headers/private/graphics/intel_extreme/
H A Dintel_extreme.h146 #define REGS_NORTH_PIPE_AND_PORT (2 << REGISTER_BLOCK_SHIFT) macro
894 #define SKL_DPLL1_CFGCR1 (0xc040 | REGS_NORTH_PIPE_AND_PORT)
895 #define SKL_DPLL1_CFGCR2 (0xc044 | REGS_NORTH_PIPE_AND_PORT)
896 #define SKL_DPLL2_CFGCR1 (0xc048 | REGS_NORTH_PIPE_AND_PORT)
897 #define SKL_DPLL2_CFGCR2 (0xc04c | REGS_NORTH_PIPE_AND_PORT)
898 #define SKL_DPLL3_CFGCR1 (0xc050 | REGS_NORTH_PIPE_AND_PORT)
899 #define SKL_DPLL3_CFGCR2 (0xc054 | REGS_NORTH_PIPE_AND_PORT)
901 #define SKL_DPLL_CTRL1 (0xc058 | REGS_NORTH_PIPE_AND_PORT)
902 #define SKL_DPLL_CTRL2 (0xc05c | REGS_NORTH_PIPE_AND_PORT)
903 #define SKL_DPLL_STATUS (0xc060 | REGS_NORTH_PIPE_AND_PORT)
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/haiku/src/add-ons/kernel/drivers/graphics/intel_extreme/
H A Dintel_extreme.cpp676 blocks[REGISTER_BLOCK(REGS_NORTH_PIPE_AND_PORT)]
688 blocks[REGISTER_BLOCK(REGS_NORTH_PIPE_AND_PORT)]
707 TRACE("REGS_NORTH_PIPE_AND_PORT: 0x%" B_PRIx32 "\n",
708 blocks[REGISTER_BLOCK(REGS_NORTH_PIPE_AND_PORT)]);

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