Searched refs:RADEON_GPU_PAGE_SIZE (Results 1 - 17 of 17) sorted by relevance

/linux-master/drivers/gpu/drm/radeon/
H A Dradeon_gart.c251 t = offset / RADEON_GPU_PAGE_SIZE;
252 p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
256 for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
297 t = offset / RADEON_GPU_PAGE_SIZE;
298 p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
304 for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
310 page_base += RADEON_GPU_PAGE_SIZE;
335 /* We need PAGE_SIZE >= RADEON_GPU_PAGE_SIZE */
336 if (PAGE_SIZE < RADEON_GPU_PAGE_SIZE) {
345 rdev->gart.num_gpu_pages = rdev->mc.gtt_size / RADEON_GPU_PAGE_SIZE;
[all...]
H A Dradeon_benchmark.c50 size / RADEON_GPU_PAGE_SIZE,
55 size / RADEON_GPU_PAGE_SIZE,
206 radeon_benchmark_move(rdev, i * RADEON_GPU_PAGE_SIZE,
213 radeon_benchmark_move(rdev, i * RADEON_GPU_PAGE_SIZE,
220 radeon_benchmark_move(rdev, i * RADEON_GPU_PAGE_SIZE,
H A Dradeon_object.h117 return bo->tbo.base.size / RADEON_GPU_PAGE_SIZE;
122 return (bo->tbo.page_alignment << PAGE_SHIFT) / RADEON_GPU_PAGE_SIZE;
H A Dradeon_vm.c466 last_pfn = eoffset / RADEON_GPU_PAGE_SIZE;
479 soffset /= RADEON_GPU_PAGE_SIZE;
480 eoffset /= RADEON_GPU_PAGE_SIZE;
552 RADEON_GPU_PAGE_SIZE, true,
773 RADEON_GPU_PAGE_SIZE, flags);
781 RADEON_GPU_PAGE_SIZE, flags);
782 addr += RADEON_GPU_PAGE_SIZE * count;
788 RADEON_GPU_PAGE_SIZE, flags | frag_flags);
792 addr += RADEON_GPU_PAGE_SIZE * count;
795 RADEON_GPU_PAGE_SIZE, flag
[all...]
H A Dradeon_test.c122 size / RADEON_GPU_PAGE_SIZE,
126 size / RADEON_GPU_PAGE_SIZE,
173 size / RADEON_GPU_PAGE_SIZE,
177 size / RADEON_GPU_PAGE_SIZE,
H A Dradeon_sa.c54 r = radeon_bo_create(rdev, size, RADEON_GPU_PAGE_SIZE, true,
H A Dradeon_ttm.c175 BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0);
177 num_pages = PFN_UP(new_mem->size) * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
H A Dradeon_uvd.c771 RADEON_GPU_PAGE_SIZE;
807 RADEON_GPU_PAGE_SIZE;
H A Dradeon_device.c464 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
494 memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);
H A Dradeon_gem.c743 args->offset = bo_va->it.start * RADEON_GPU_PAGE_SIZE;
H A Dradeon.h595 #define RADEON_GPU_PAGE_SIZE 4096 macro
596 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
H A Dsi.c3650 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3681 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3705 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
H A Dni.c1669 rb_cntl |= order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8;
H A Dr600.c1511 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
2730 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
H A Dr100.c909 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
H A Dcik.c4070 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
4665 (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8);
H A Devergreen.c3083 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;

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