/linux-master/drivers/gpu/drm/nouveau/dispnv50/ |
H A D | crcc57d.c | 40 PUSH_MTHD(push, NVC57D, HEAD_SET_CONTEXT_DMA_CRC(i), ctx->ntfy.handle); 41 PUSH_MTHD(push, NVC57D, HEAD_SET_CRC_CONTROL(i), crc_args); 43 PUSH_MTHD(push, NVC57D, HEAD_SET_CRC_CONTROL(i), 0); 44 PUSH_MTHD(push, NVC57D, HEAD_SET_CONTEXT_DMA_CRC(i), 0);
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H A D | dac907d.c | 38 PUSH_MTHD(push, NV907D, DAC_SET_CONTROL(or), ctrl);
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H A D | corec57d.c | 39 PUSH_MTHD(push, NVC57D, SET_CONTEXT_DMA_NOTIFIER, core->chan.sync.handle); 42 PUSH_MTHD(push, NVC57D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(i), 50 PUSH_MTHD(push, NVC57D, WINDOW_SET_WINDOW_USAGE_BOUNDS(i),
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H A D | ovly907e.c | 38 PUSH_MTHD(push, NV907E, SET_PRESENT_CONTROL, 42 PUSH_MTHD(push, NV907E, SET_CONTEXT_DMA_ISO, asyw->image.handle[0]); 44 PUSH_MTHD(push, NV907E, SET_COMPOSITION_CONTROL, 47 PUSH_MTHD(push, NV907E, SURFACE_SET_OFFSET, asyw->image.offset[0] >> 8); 49 PUSH_MTHD(push, NV907E, SURFACE_SET_SIZE,
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H A D | ovly827e.c | 41 PUSH_MTHD(push, NV827E, SET_PRESENT_CONTROL, 45 PUSH_MTHD(push, NV827E, SET_CONTEXT_DMA_ISO, asyw->image.handle[0]); 47 PUSH_MTHD(push, NV827E, SET_COMPOSITION_CONTROL, 50 PUSH_MTHD(push, NV827E, SURFACE_SET_OFFSET, asyw->image.offset[0] >> 8); 52 PUSH_MTHD(push, NV827E, SURFACE_SET_SIZE,
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H A D | base827c.c | 37 PUSH_MTHD(push, NV827C, SET_PRESENT_CONTROL, 41 PUSH_MTHD(push, NV827C, SET_CONTEXT_DMAS_ISO(0), asyw->image.handle, 1); 44 PUSH_MTHD(push, NV827C, SET_PROCESSING, 51 PUSH_MTHD(push, NV827C, SET_PROCESSING, 59 PUSH_MTHD(push, NV827C, SURFACE_SET_OFFSET(0, 0), asyw->image.offset[0] >> 8,
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H A D | head827d.c | 39 PUSH_MTHD(push, NV827D, HEAD_SET_CONTROL_CURSOR(i), 44 PUSH_MTHD(push, NV827D, HEAD_SET_CONTEXT_DMA_CURSOR(i), 0x00000000); 58 PUSH_MTHD(push, NV827D, HEAD_SET_CONTROL_CURSOR(i), 69 PUSH_MTHD(push, NV827D, HEAD_SET_CONTEXT_DMA_CURSOR(i), asyh->curs.handle); 83 PUSH_MTHD(push, NV827D, HEAD_SET_OFFSET(i, 0), 86 PUSH_MTHD(push, NV827D, HEAD_SET_SIZE(i), 104 PUSH_MTHD(push, NV827D, HEAD_SET_VIEWPORT_POINT_IN(i, 0), 120 PUSH_MTHD(push, NV827D, HEAD_SET_BASE_LUT_LO(i), 123 PUSH_MTHD(push, NV827D, HEAD_SET_CONTEXT_DMA_LUT(i), 0x00000000); 137 PUSH_MTHD(pus [all...] |
H A D | wndwc57e.c | 41 PUSH_MTHD(push, NVC57E, SET_PRESENT_CONTROL, 46 PUSH_MTHD(push, NVC57E, SET_SIZE, 64 PUSH_MTHD(push, NVC57E, SET_CONTEXT_DMA_ISO(0), asyw->image.handle, 1); 65 PUSH_MTHD(push, NVC57E, SET_OFFSET(0), asyw->image.offset[0] >> 8); 67 PUSH_MTHD(push, NVC57E, SET_POINT_IN(0), 71 PUSH_MTHD(push, NVC57E, SET_SIZE_IN, 75 PUSH_MTHD(push, NVC57E, SET_SIZE_OUT, 95 PUSH_MTHD(push, NVC57E, SET_FMT_COEFFICIENT_C00, identity, ARRAY_SIZE(identity)); 108 PUSH_MTHD(push, NVC57E, SET_FMT_COEFFICIENT_C00, asyw->csc.matrix, 12); 121 PUSH_MTHD(pus [all...] |
H A D | wndwc67e.c | 38 PUSH_MTHD(push, NVC57E, SET_PRESENT_CONTROL, 43 PUSH_MTHD(push, NVC57E, SET_SIZE, 60 PUSH_MTHD(push, NVC57E, SET_CONTEXT_DMA_ISO(0), asyw->image.handle, 1); 61 PUSH_MTHD(push, NVC57E, SET_OFFSET(0), asyw->image.offset[0] >> 8); 63 PUSH_MTHD(push, NVC57E, SET_POINT_IN(0), 67 PUSH_MTHD(push, NVC57E, SET_SIZE_IN, 71 PUSH_MTHD(push, NVC57E, SET_SIZE_OUT,
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H A D | wndwc37e.c | 48 PUSH_MTHD(push, NVC37E, SET_CSC_RED2RED, asyw->csc.matrix, 12); 61 PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_INPUT_LUT, 0x00000000); 74 PUSH_MTHD(push, NVC37E, SET_CONTROL_INPUT_LUT, 103 PUSH_MTHD(push, NVC37E, SET_COMPOSITION_CONTROL, 148 PUSH_MTHD(push, NVC37E, SET_PRESENT_CONTROL, 152 PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_ISO(0), 0x00000000); 165 PUSH_MTHD(push, NVC37E, SET_PRESENT_CONTROL, 170 PUSH_MTHD(push, NVC37E, SET_SIZE, 192 PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_ISO(0), asyw->image.handle, 1); 193 PUSH_MTHD(pus [all...] |
H A D | base907c.c | 37 PUSH_MTHD(push, NV907C, SET_PRESENT_CONTROL, 42 PUSH_MTHD(push, NV907C, SET_CONTEXT_DMAS_ISO(0), asyw->image.handle, 1); 44 PUSH_MTHD(push, NV907C, SURFACE_SET_OFFSET(0, 0), asyw->image.offset[0] >> 8, 74 PUSH_MTHD(push, NV907C, SET_BASE_LUT_LO, 77 PUSH_MTHD(push, NV907C, SET_OUTPUT_LUT_LO, 80 PUSH_MTHD(push, NV907C, SET_CONTEXT_DMA_LUT, 0x00000000); 93 PUSH_MTHD(push, NV907C, SET_BASE_LUT_LO, 102 PUSH_MTHD(push, NV907C, SET_CONTEXT_DMA_LUT, asyw->xlut.handle); 165 PUSH_MTHD(push, NV907C, SET_CSC_RED2RED, 179 PUSH_MTHD(pus [all...] |
H A D | core507d.c | 43 PUSH_MTHD(push, NV507D, SET_NOTIFIER_CONTROL, 49 PUSH_MTHD(push, NV507D, UPDATE, interlock[NV50_DISP_INTERLOCK_BASE] | 90 PUSH_MTHD(push, NV507D, SET_NOTIFIER_CONTROL, 95 PUSH_MTHD(push, NV507D, GET_CAPABILITIES, 0x00000000); 97 PUSH_MTHD(push, NV507D, SET_NOTIFIER_CONTROL, 139 PUSH_MTHD(push, NV507D, SET_CONTEXT_DMA_NOTIFIER, core->chan.sync.handle);
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H A D | sorc37d.c | 38 PUSH_MTHD(push, NVC37D, SOR_SET_CONTROL(or), ctrl);
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H A D | headc37d.c | 55 PUSH_MTHD(push, NVC37D, HEAD_SET_CONTROL_OUTPUT_RESOURCE(i), 74 PUSH_MTHD(push, NVC37D, HEAD_SET_PROCAMP(i), 95 PUSH_MTHD(push, NVC37D, HEAD_SET_DITHER_CONTROL(i), 114 PUSH_MTHD(push, NVC37D, HEAD_SET_CONTROL_CURSOR(i), 118 PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CURSOR(i, 0), 0x00000000); 132 PUSH_MTHD(push, NVC37D, HEAD_SET_CONTROL_CURSOR(i), 148 PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CURSOR(i, 0), asyh->curs.handle); 149 PUSH_MTHD(push, NVC37D, HEAD_SET_OFFSET_CURSOR(i, 0), asyh->curs.offset >> 8); 171 PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_OUTPUT_LUT(i), 0x00000000); 185 PUSH_MTHD(pus [all...] |
H A D | head907d.c | 46 PUSH_MTHD(push, NV907D, HEAD_SET_CONTROL_OUTPUT_RESOURCE(i), 67 PUSH_MTHD(push, NV907D, HEAD_SET_PROCAMP(i), 87 PUSH_MTHD(push, NV907D, HEAD_SET_DITHER_CONTROL(i), 120 PUSH_MTHD(push, NV907D, HEAD_SET_OVERLAY_USAGE_BOUNDS(i), bounds); 148 PUSH_MTHD(push, NV907D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(i), bounds); 162 PUSH_MTHD(push, NV907D, HEAD_SET_CONTROL_CURSOR(i), 167 PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CURSOR(i), 0x00000000); 181 PUSH_MTHD(push, NV907D, HEAD_SET_CONTROL_CURSOR(i), 191 PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CURSOR(i), asyh->curs.handle); 205 PUSH_MTHD(pus [all...] |
H A D | base507c.c | 44 PUSH_MTHD(push, NV507C, UPDATE, interlock[NV50_DISP_INTERLOCK_CORE]); 57 PUSH_MTHD(push, NV507C, SET_PRESENT_CONTROL, 61 PUSH_MTHD(push, NV507C, SET_CONTEXT_DMA_ISO, 0x00000000); 74 PUSH_MTHD(push, NV507C, SET_PRESENT_CONTROL, 78 PUSH_MTHD(push, NV507C, SET_CONTEXT_DMA_ISO, asyw->image.handle[0]); 81 PUSH_MTHD(push, NV507C, SET_PROCESSING, 88 PUSH_MTHD(push, NV507C, SET_PROCESSING, 96 PUSH_MTHD(push, NV507C, SURFACE_SET_OFFSET(0, 0), asyw->image.offset[0] >> 8); 98 PUSH_MTHD(push, NV507C, SURFACE_SET_SIZE(0), 127 PUSH_MTHD(pus [all...] |
H A D | corec37d.c | 44 PUSH_MTHD(push, NVC37D, WINDOW_SET_CONTROL(i), 61 PUSH_MTHD(push, NVC37D, SET_NOTIFIER_CONTROL, 67 PUSH_MTHD(push, NVC37D, SET_INTERLOCK_FLAGS, interlock[NV50_DISP_INTERLOCK_CURS], 69 PUSH_MTHD(push, NVC37D, UPDATE, 0x00000001 | 74 PUSH_MTHD(push, NVC37D, SET_NOTIFIER_CONTROL, 137 PUSH_MTHD(push, NVC37D, SET_CONTEXT_DMA_NOTIFIER, core->chan.sync.handle); 140 PUSH_MTHD(push, NVC37D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(i), 149 PUSH_MTHD(push, NVC37D, WINDOW_SET_WINDOW_USAGE_BOUNDS(i),
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H A D | crcc37d.c | 44 PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CRC(i), ctx->ntfy.handle); 45 PUSH_MTHD(push, NVC37D, HEAD_SET_CRC_CONTROL(i), crc_args); 47 PUSH_MTHD(push, NVC37D, HEAD_SET_CRC_CONTROL(i), 0); 48 PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CRC(i), 0); 63 PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CRC(i), ctx ? ctx->ntfy.handle : 0);
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H A D | crc907d.c | 64 PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CRC(i), ctx->ntfy.handle); 65 PUSH_MTHD(push, NV907D, HEAD_SET_CRC_CONTROL(i), crc_args); 67 PUSH_MTHD(push, NV907D, HEAD_SET_CRC_CONTROL(i), crc_args); 68 PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CRC(i), 0); 84 PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CRC(i), ctx ? ctx->ntfy.handle : 0);
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H A D | head507d.c | 39 PUSH_MTHD(push, NV507D, HEAD_SET_PROCAMP(i), 58 PUSH_MTHD(push, NV507D, HEAD_SET_DITHER_CONTROL(i), 90 PUSH_MTHD(push, NV507D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(i), bounds); 118 PUSH_MTHD(push, NV507D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(i), bounds); 132 PUSH_MTHD(push, NV507D, HEAD_SET_CONTROL_CURSOR(i), 149 PUSH_MTHD(push, NV507D, HEAD_SET_CONTROL_CURSOR(i), 198 PUSH_MTHD(push, NV507D, HEAD_SET_CONTEXT_DMA_ISO(i), 0x00000000); 212 PUSH_MTHD(push, NV507D, HEAD_SET_OFFSET(i, 0), 215 PUSH_MTHD(push, NV507D, HEAD_SET_SIZE(i), 233 PUSH_MTHD(pus [all...] |
H A D | pior507d.c | 45 PUSH_MTHD(push, NV507D, PIOR_SET_CONTROL(or), ctrl);
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H A D | sor907d.c | 41 PUSH_MTHD(push, NV907D, SOR_SET_CONTROL(or), ctrl);
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/linux-master/drivers/gpu/drm/nouveau/ |
H A D | nouveau_bo0039.c | 62 PUSH_MTHD(push, NV039, SET_CONTEXT_DMA_BUFFER_IN, src_ctxdma, 73 PUSH_MTHD(push, NV039, OFFSET_IN, src_offset, 86 PUSH_MTHD(push, NV039, NO_OPERATION, 0x00000000); 106 PUSH_MTHD(push, NV039, SET_OBJECT, handle); 107 PUSH_MTHD(push, NV039, SET_CONTEXT_DMA_NOTIFIES, chan->drm->ntfy.handle);
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H A D | nouveau_bo5039.c | 63 PUSH_MTHD(push, NV5039, SET_SRC_MEMORY_LAYOUT, 80 PUSH_MTHD(push, NV5039, SET_SRC_MEMORY_LAYOUT, 85 PUSH_MTHD(push, NV5039, SET_DST_MEMORY_LAYOUT, 102 PUSH_MTHD(push, NV5039, SET_DST_MEMORY_LAYOUT, 106 PUSH_MTHD(push, NV5039, OFFSET_IN_UPPER, 112 PUSH_MTHD(push, NV5039, OFFSET_IN, lower_32_bits(src_offset), 126 PUSH_MTHD(push, NV5039, NO_OPERATION, 0x00000000); 146 PUSH_MTHD(push, NV5039, SET_OBJECT, handle); 147 PUSH_MTHD(push, NV5039, SET_CONTEXT_DMA_NOTIFY, chan->drm->ntfy.handle,
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H A D | nouveau_bo9039.c | 56 PUSH_MTHD(push, NV9039, OFFSET_OUT_UPPER, 61 PUSH_MTHD(push, NV9039, OFFSET_IN_UPPER, 70 PUSH_MTHD(push, NV9039, LAUNCH_DMA, 96 PUSH_MTHD(push, NV9039, SET_OBJECT, handle);
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