Searched refs:PSC (Results 1 - 3 of 3) sorted by path
| /linux-master/arch/powerpc/platforms/512x/ |
| H A D | clock-commonclk.c | 89 * interpretation, no CFM, different fourth PSC/CAN mux0 input -- yet
471 * suggests that all instances of the "PSC clock generation" are equal,
472 * and that one might re-use the PSC setup for MSCAN clock generation
594 /* setup the MCLK clock subtree of an individual PSC/MSCAN/SPDIF */
663 * the PSC/MSCAN/SPDIF (serial drivers et al) need the MCLK
720 * - PSC/MSCAN/SPDIF clock generation OTOH already is very
861 /* MSCAN differs from PSC with just one gate for multiple components */
1040 NODE_CHK("ipg", clks[MPC512x_CLK_PSC0 + idx], 0, PSC);
1041 NODE_CHK("mclk", clks[MPC512x_CLK_PSC0_MCLK + idx], 0, PSC);
1158 (did_register & DID_REG_PSC) ? " PSC"
[all...] |
| /linux-master/drivers/mfd/ |
| H A D | mt6358-irq.c | 24 MT6357_TOP_GEN(PSC),
35 MT6358_TOP_GEN(PSC),
46 MT6359_TOP_GEN(PSC),
|
| /linux-master/drivers/tty/serial/ |
| H A D | mpc52xx_uart.c | 3 * Driver for the PSC of the Freescale MPC52xx PSCs configured as UARTs.
75 #define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase)) macro
83 /* PSC fifo operations for isolating differences between 52xx and 512x */
135 return in_be16(&PSC(port)->mpc52xx_psc_status);
140 return in_8(&PSC(port)->mpc52xx_psc_ipcr);
145 out_8(&PSC(port)->command, cmd);
150 out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1);
151 out_8(&PSC(port)->mode, mr1);
152 out_8(&PSC(port)->mode, mr2);
158 out_8(&PSC(por
[all...] |
Completed in 340 milliseconds