Searched refs:PSB_WVDC32 (Results 1 - 8 of 8) sorted by relevance

/linux-master/drivers/gpu/drm/gma500/
H A Doaktrail_device.c204 PSB_WVDC32(0, PP_CONTROL);
211 PSB_WVDC32(0x58000000, DSPACNTR);
213 PSB_WVDC32(0, DSPASURF);
219 PSB_WVDC32(0x0, PIPEACONF);
224 PSB_WVDC32(0, MRST_DPLL_A);
244 PSB_WVDC32(regs->psb.saveDSPARB, DSPARB);
245 PSB_WVDC32(regs->psb.saveDSPFW1, DSPFW1);
246 PSB_WVDC32(regs->psb.saveDSPFW2, DSPFW2);
247 PSB_WVDC32(regs->psb.saveDSPFW3, DSPFW3);
248 PSB_WVDC32(reg
[all...]
H A Dpsb_irq.c55 PSB_WVDC32(writeVal, reg);
70 PSB_WVDC32(writeVal, reg);
102 PSB_WVDC32(PSB_RVDC32(pipe_stat_reg), pipe_stat_reg);
239 PSB_WVDC32(vdc_stat, PSB_INT_IDENTITY_R);
256 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
257 PSB_WVDC32(0x00000000, PSB_INT_MASK_R);
258 PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R);
273 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
291 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
292 PSB_WVDC32(
[all...]
H A Dpsb_device.c157 PSB_WVDC32(regs->saveDSPARB, DSPARB);
158 PSB_WVDC32(regs->saveDSPFW1, DSPFW1);
159 PSB_WVDC32(regs->saveDSPFW2, DSPFW2);
160 PSB_WVDC32(regs->saveDSPFW3, DSPFW3);
161 PSB_WVDC32(regs->saveDSPFW4, DSPFW4);
162 PSB_WVDC32(regs->saveDSPFW5, DSPFW5);
163 PSB_WVDC32(regs->saveDSPFW6, DSPFW6);
164 PSB_WVDC32(regs->saveCHICKENBIT, DSPCHICKENBIT);
167 PSB_WVDC32(0x80000000, VGACNTRL);
H A Doaktrail_hdmi.c800 PSB_WVDC32(hdmi_dev->saveDPLL_CTRL, DPLL_CTRL);
801 PSB_WVDC32(hdmi_dev->saveDPLL_DIV_CTRL, DPLL_DIV_CTRL);
802 PSB_WVDC32(hdmi_dev->saveDPLL_ADJUST, DPLL_ADJUST);
803 PSB_WVDC32(hdmi_dev->saveDPLL_UPDATE, DPLL_UPDATE);
804 PSB_WVDC32(hdmi_dev->saveDPLL_CLK_ENABLE, DPLL_CLK_ENABLE);
808 PSB_WVDC32(pipeb->src, PIPEBSRC);
809 PSB_WVDC32(pipeb->htotal, HTOTAL_B);
810 PSB_WVDC32(pipeb->hblank, HBLANK_B);
811 PSB_WVDC32(pipeb->hsync, HSYNC_B);
812 PSB_WVDC32(pipe
[all...]
H A Dpower.c118 PSB_WVDC32(dev_priv->pge_ctl | _PSB_PGETBL_ENABLED, PSB_PGETBL_CTL);
H A Dgtt.c142 PSB_WVDC32(dev_priv->pge_ctl | _PSB_PGETBL_ENABLED, PSB_PGETBL_CTL);
155 PSB_WVDC32(dev_priv->pge_ctl, PSB_PGETBL_CTL);
H A Dpsb_drv.c379 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
380 PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R);
381 PSB_WVDC32(0xFFFFFFFF, PSB_INT_MASK_R);
H A Dpsb_drv.h719 #define PSB_WVDC32(_val, _offs) iowrite32(_val, dev_priv->vdc_reg + (_offs)) macro

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