Searched refs:PHYCLKD32PerState (Results 1 - 6 of 6) sorted by relevance
| /linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | display_mode_vba_util_32.h | 252 double PHYCLKD32PerState,
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| H A D | display_mode_vba_util_32.c | 1339 double PHYCLKD32PerState,
1404 PHYCLKD32PerState >= 10000 / 32) {
1410 if (*OutBpp == 0 && PHYCLKD32PerState < 13500 / 32 && DSCEnable == true &&
1426 *OutBpp == 0 && PHYCLKD32PerState >= 13500 / 32) {
1433 if (*OutBpp == 0 && PHYCLKD32PerState < 20000 / 32 && DSCEnable == true &&
1449 *OutBpp == 0 && PHYCLKD32PerState >= 20000 / 32) {
1336 dml32_CalculateOutputLink( double PHYCLKPerState, double PHYCLKD18PerState, double PHYCLKD32PerState, double Downspreading, bool IsMainSurfaceUsingTheIndicatedTiming, enum output_encoder_class Output, enum output_format_class OutputFormat, unsigned int HTotal, unsigned int HActive, double PixelClockBackEnd, double ForcedOutputLinkBPP, unsigned int DSCInputBitPerComponent, unsigned int NumberOfDSCSlices, double AudioSampleRate, unsigned int AudioSampleLayout, enum odm_combine_mode ODMModeNoDSC, enum odm_combine_mode ODMModeDSC, bool DSCEnable, unsigned int OutputLinkDPLanes, enum dm_output_link_dp_rate OutputLinkDPRate, bool *RequiresDSC, double *RequiresFEC, double *OutBpp, enum dm_output_type *OutputType, enum dm_output_rate *OutputRate, unsigned int *RequiredSlots) argument
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| H A D | display_mode_vba_32.c | 2090 mode_lib->vba.PHYCLKD32PerState[i],
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| /linux-master/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_vba.h | 610 double PHYCLKD32PerState[DC__VOLTAGE_STATES]; member in struct:vba_vars_st
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| H A D | display_mode_vba.c | 400 mode_lib->vba.PHYCLKD32PerState[i] = soc->clock_limits[i].phyclk_d32_mhz;
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| /linux-master/drivers/gpu/drm/amd/display/dc/dml2/ |
| H A D | display_mode_core.c | 76 dml_float_t PHYCLKD32PerState,
5341 dml_float_t PHYCLKD32PerState,
5406 if ((OutputLinkDPRate == dml_dp_rate_na || OutputLinkDPRate == dml_dp_rate_uhbr10) && PHYCLKD32PerState >= 10000 / 32) {
5409 if (*OutBpp == 0 && PHYCLKD32PerState < 13500 / 32 && DSCEnable == dml_dsc_enable_if_necessary && ForcedOutputLinkBPP == 0) {
5419 if ((OutputLinkDPRate == dml_dp_rate_na || OutputLinkDPRate == dml_dp_rate_uhbr13p5) && *OutBpp == 0 && PHYCLKD32PerState >= 13500 / 32) {
5423 if (*OutBpp == 0 && PHYCLKD32PerState < 20000 / 32 && DSCEnable == dml_dsc_enable_if_necessary && ForcedOutputLinkBPP == 0) {
5433 if ((OutputLinkDPRate == dml_dp_rate_na || OutputLinkDPRate == dml_dp_rate_uhbr20) && *OutBpp == 0 && PHYCLKD32PerState >= 20000 / 32) {
5338 CalculateOutputLink( dml_float_t PHYCLKPerState, dml_float_t PHYCLKD18PerState, dml_float_t PHYCLKD32PerState, dml_float_t Downspreading, dml_bool_t IsMainSurfaceUsingTheIndicatedTiming, enum dml_output_encoder_class Output, enum dml_output_format_class OutputFormat, dml_uint_t HTotal, dml_uint_t HActive, dml_float_t PixelClockBackEnd, dml_float_t ForcedOutputLinkBPP, dml_uint_t DSCInputBitPerComponent, dml_uint_t NumberOfDSCSlices, dml_float_t AudioSampleRate, dml_uint_t AudioSampleLayout, enum dml_odm_mode ODMModeNoDSC, enum dml_odm_mode ODMModeDSC, enum dml_dsc_enable DSCEnable, dml_uint_t OutputLinkDPLanes, enum dml_output_link_dp_rate OutputLinkDPRate, dml_bool_t *RequiresDSC, dml_bool_t *RequiresFEC, dml_float_t *OutBpp, enum dml_output_type_and_rate__type *OutputType, enum dml_output_type_and_rate__rate *OutputRate, dml_uint_t *RequiredSlots) argument
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Completed in 308 milliseconds