Searched refs:PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_K2 (Results 1 - 1 of 1) sorted by last modified time

/freebsd-11-stable/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h2396 #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_K2 (0xf<<24) // Upstream Port 8.0 GT/s Transmitter Preset 1. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS macro
[all...]

Completed in 1575 milliseconds