Searched refs:PCIEIP_REG_REG_L1SUB_CAP_BB (Results 1 - 1 of 1) sorted by path

/freebsd-11-stable/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h5041 #define PCIEIP_REG_REG_L1SUB_CAP_BB 0x000540UL //Access:RW DataWidth:0x20 // Multi Field Register. macro
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