Searched refs:PCIEIP_REG_PCIEEP_RAS_SD_EQ_CTL1_EQ_RATE_SEL_E5 (Results 1 - 1 of 1) sorted by last modified time

/freebsd-11-stable/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h4302 #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_CTL1_EQ_RATE_SEL_E5 (0x1<<4) // EQ status rate select. Setting this field in conjunction with [EQ_LANE_SEL] determines the per-lane silicon debug EQ status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. 0x0 = 8.0 GT/s speed. 0x1 = 16.0 GT/s speed. macro
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