Searched refs:PCIEIP_REG_PCIEEP_RAS_EINJ_CTL2_EINJ2_DLLP_TYPE_E5 (Results 1 - 1 of 1) sorted by last modified time

/freebsd-11-stable/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h3920 #define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL2_EINJ2_DLLP_TYPE_E5 (0x3<<8) // DLLP type. Selects the type of DLLP errors to be inserted. 0x0 = ACK/NAK DLLP transmission block. 0x1 = Update FC DLLP's transmission block. 0x2 = Always transmission for NAK DLLP. 0x3 = Reserved. macro
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