Searched refs:PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT10_MPL_E5 (Results 1 - 1 of 1) sorted by path
| /freebsd-11-stable/sys/dev/qlnx/qlnxe/ | ||
| H A D | reg_addr.h | 2998 #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT10_MPL_E5 (0xff<<8) // Margin payload for this lane. macro [all...] |
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