Searched refs:PCIEIP_REG_LINK_STATUS_CONTROL_SLOT_CLK_CONFIG_BB (Results 1 - 1 of 1) sorted by path

/freebsd-11-stable/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h1319 #define PCIEIP_REG_LINK_STATUS_CONTROL_SLOT_CLK_CONFIG_BB (0x1<<28) // Slot Clock configuration. This bit is read-only by host, but read/write via backdoor CS bus. Path= i_cfg_func.i_cfg_private macro
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