Searched refs:PCIEIP_REG_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY_BB (Results 1 - 1 of 1) sorted by last modified time

/freebsd-11-stable/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h1192 #define PCIEIP_REG_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY_BB (0x7<<9) // Endpoint L1 Acceptable Latency. These bits are programmable through register space. The bits should be 0 for Root ports Path= i_cfg_func.i_cfg_private macro
[all...]

Completed in 1057 milliseconds