Searched refs:PCIEIP_REG_BAR5_REG_K2 (Results 1 - 1 of 1) sorted by last modified time

/freebsd-11-stable/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h400 #define PCIEIP_REG_BAR5_REG_K2 0x000024UL //Access:RW DataWidth:0x20 // BAR5 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". macro
[all...]

Completed in 1389 milliseconds