Searched refs:OUTREG8 (Results 1 - 12 of 12) sorted by relevance
/haiku/src/add-ons/accelerants/s3/ |
H A D | register_io.cpp | 21 #define OUTREG8(addr, val) *((vuint8*)(gInfo.regs + addr)) = val macro 97 OUTREG8(addr, value); 129 OUTREG8(0x83d4, index); 140 OUTREG8(0x83d4, index); 141 OUTREG8(0x83d5, value); 155 OUTREG8(0x83d4, index); 156 OUTREG8(0x83d5, (INREG8(0x83d5) & ~mask) | (value & mask)); 171 OUTREG8(0x83c4, index); 182 OUTREG8(0x83c4, index); 183 OUTREG8( [all...] |
/haiku/src/add-ons/accelerants/intel_810/ |
H A D | i810_regs.h | 115 #define OUTREG8(addr, val) (*((vuint8*)(gInfo.regs + (addr))) = (val)) macro 128 OUTREG8(CRTC_INDEX, index); 136 OUTREG8(CRTC_INDEX, index); 137 OUTREG8(CRTC_DATA, value); 144 OUTREG8(GRAPH_INDEX, index); 152 OUTREG8(GRAPH_INDEX, index); 153 OUTREG8(GRAPH_DATA, value); 160 OUTREG8(SEQ_INDEX, index); 168 OUTREG8(SEQ_INDEX, index); 169 OUTREG8(SEQ_DAT [all...] |
H A D | i810_mode.cpp | 183 OUTREG8(DRAM_ROW_CNTL_HI, temp | DRAM_REFRESH_DISABLE); 195 OUTREG8(VCLK2_VCO_DIV_SEL, p); 206 OUTREG8(MISC_OUT_W, miscOutReg); 222 OUTREG8(DRAM_ROW_CNTL_HI, temp | DRAM_REFRESH_60HZ); 226 OUTREG8(BITBLT_CNTL, temp); 278 OUTREG8(DAC_MASK, 0xff); 279 OUTREG8(DAC_W_INDEX, first); // initial color index 282 OUTREG8(DAC_DATA, colorData[0]); // red 283 OUTREG8(DAC_DATA, colorData[1]); // green 284 OUTREG8(DAC_DAT [all...] |
H A D | i810_dpms.cpp | 98 OUTREG8(DPMS_SYNC_SELECT, dpmsSyncSelect); // set DPMS mode
|
/haiku/headers/private/graphics/radeon/ |
H A D | mmio.h | 16 #define OUTREG8( regs, addr, val ) do { *(regs + (addr)) = (val); } while( 0 ) macro
|
/haiku/src/add-ons/accelerants/ati/ |
H A D | mach64_mode.cpp | 105 OUTREG8(CLOCK_CNTL, clkNum | CLOCK_STROBE); 356 OUTREG8(DAC_MASK, 0xff); 357 OUTREG8(DAC_W_INDEX, 0); // initial color index 360 OUTREG8(DAC_DATA, i); 361 OUTREG8(DAC_DATA, i); 362 OUTREG8(DAC_DATA, i); 400 OUTREG8(DAC_MASK, 0xff); 401 OUTREG8(DAC_W_INDEX, first); // initial color index 404 OUTREG8(DAC_DATA, colorData[0]); // red 405 OUTREG8(DAC_DAT [all...] |
H A D | mach64.h | 480 OUTREG8(CLOCK_CNTL + 1, (index << 2) & PLL_ADDR); 488 OUTREG8(CLOCK_CNTL + 1, ((index << 2) & PLL_ADDR) | PLL_WR_EN); 489 OUTREG8(CLOCK_CNTL + 2, value); 496 OUTREG8(LCD_INDEX, index & LCD_REG_INDEX); 504 OUTREG8(LCD_INDEX, index & LCD_REG_INDEX);
|
H A D | rage128.h | 282 OUTREG8(R128_CLOCK_CNTL_INDEX, index & 0x3f); 290 OUTREG8(R128_CLOCK_CNTL_INDEX, ((index) & 0x3f) | R128_PLL_WR_EN);
|
H A D | rage128_mode.cpp | 395 OUTREG8(R128_PALETTE_INDEX, 0); // set first color index 438 OUTREG8(R128_PALETTE_INDEX, first); // set first color index
|
H A D | accelerant.h | 240 #define OUTREG8(addr, val) *((vuint8*)(gInfo.regs + addr)) = val macro
|
/haiku/src/add-ons/kernel/drivers/graphics/radeon/ |
H A D | pll_access.c | 63 OUTREG8( regs, RADEON_CLOCK_CNTL_INDEX, addr & 0x3f ); 75 OUTREG8( regs, RADEON_CLOCK_CNTL_INDEX, ((addr & 0x3f ) |
|
/haiku/src/add-ons/accelerants/3dfx/ |
H A D | accelerant.h | 181 #define OUTREG8(addr, val) *((vuint8*)(gInfo.regs + addr)) = val macro
|
Completed in 63 milliseconds