Searched refs:OUTREG8 (Results 1 - 12 of 12) sorted by relevance

/haiku/src/add-ons/accelerants/s3/
H A Dregister_io.cpp21 #define OUTREG8(addr, val) *((vuint8*)(gInfo.regs + addr)) = val macro
97 OUTREG8(addr, value);
129 OUTREG8(0x83d4, index);
140 OUTREG8(0x83d4, index);
141 OUTREG8(0x83d5, value);
155 OUTREG8(0x83d4, index);
156 OUTREG8(0x83d5, (INREG8(0x83d5) & ~mask) | (value & mask));
171 OUTREG8(0x83c4, index);
182 OUTREG8(0x83c4, index);
183 OUTREG8(
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/haiku/src/add-ons/accelerants/intel_810/
H A Di810_regs.h115 #define OUTREG8(addr, val) (*((vuint8*)(gInfo.regs + (addr))) = (val)) macro
128 OUTREG8(CRTC_INDEX, index);
136 OUTREG8(CRTC_INDEX, index);
137 OUTREG8(CRTC_DATA, value);
144 OUTREG8(GRAPH_INDEX, index);
152 OUTREG8(GRAPH_INDEX, index);
153 OUTREG8(GRAPH_DATA, value);
160 OUTREG8(SEQ_INDEX, index);
168 OUTREG8(SEQ_INDEX, index);
169 OUTREG8(SEQ_DAT
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H A Di810_mode.cpp183 OUTREG8(DRAM_ROW_CNTL_HI, temp | DRAM_REFRESH_DISABLE);
195 OUTREG8(VCLK2_VCO_DIV_SEL, p);
206 OUTREG8(MISC_OUT_W, miscOutReg);
222 OUTREG8(DRAM_ROW_CNTL_HI, temp | DRAM_REFRESH_60HZ);
226 OUTREG8(BITBLT_CNTL, temp);
278 OUTREG8(DAC_MASK, 0xff);
279 OUTREG8(DAC_W_INDEX, first); // initial color index
282 OUTREG8(DAC_DATA, colorData[0]); // red
283 OUTREG8(DAC_DATA, colorData[1]); // green
284 OUTREG8(DAC_DAT
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H A Di810_dpms.cpp98 OUTREG8(DPMS_SYNC_SELECT, dpmsSyncSelect); // set DPMS mode
/haiku/headers/private/graphics/radeon/
H A Dmmio.h16 #define OUTREG8( regs, addr, val ) do { *(regs + (addr)) = (val); } while( 0 ) macro
/haiku/src/add-ons/accelerants/ati/
H A Dmach64_mode.cpp105 OUTREG8(CLOCK_CNTL, clkNum | CLOCK_STROBE);
356 OUTREG8(DAC_MASK, 0xff);
357 OUTREG8(DAC_W_INDEX, 0); // initial color index
360 OUTREG8(DAC_DATA, i);
361 OUTREG8(DAC_DATA, i);
362 OUTREG8(DAC_DATA, i);
400 OUTREG8(DAC_MASK, 0xff);
401 OUTREG8(DAC_W_INDEX, first); // initial color index
404 OUTREG8(DAC_DATA, colorData[0]); // red
405 OUTREG8(DAC_DAT
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H A Dmach64.h480 OUTREG8(CLOCK_CNTL + 1, (index << 2) & PLL_ADDR);
488 OUTREG8(CLOCK_CNTL + 1, ((index << 2) & PLL_ADDR) | PLL_WR_EN);
489 OUTREG8(CLOCK_CNTL + 2, value);
496 OUTREG8(LCD_INDEX, index & LCD_REG_INDEX);
504 OUTREG8(LCD_INDEX, index & LCD_REG_INDEX);
H A Drage128.h282 OUTREG8(R128_CLOCK_CNTL_INDEX, index & 0x3f);
290 OUTREG8(R128_CLOCK_CNTL_INDEX, ((index) & 0x3f) | R128_PLL_WR_EN);
H A Drage128_mode.cpp395 OUTREG8(R128_PALETTE_INDEX, 0); // set first color index
438 OUTREG8(R128_PALETTE_INDEX, first); // set first color index
H A Daccelerant.h240 #define OUTREG8(addr, val) *((vuint8*)(gInfo.regs + addr)) = val macro
/haiku/src/add-ons/kernel/drivers/graphics/radeon/
H A Dpll_access.c63 OUTREG8( regs, RADEON_CLOCK_CNTL_INDEX, addr & 0x3f );
75 OUTREG8( regs, RADEON_CLOCK_CNTL_INDEX, ((addr & 0x3f ) |
/haiku/src/add-ons/accelerants/3dfx/
H A Daccelerant.h181 #define OUTREG8(addr, val) *((vuint8*)(gInfo.regs + addr)) = val macro

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