Searched refs:OUTREG32 (Results 1 - 12 of 12) sorted by relevance

/haiku/src/add-ons/accelerants/3dfx/
H A D3dfx_draw.cpp34 OUTREG32(DST_FORMAT, fmt);
35 OUTREG32(COLOR_BACK, color);
36 OUTREG32(COLOR_FORE, color);
45 OUTREG32(DST_SIZE, w | (h << 16));
46 OUTREG32(DST_XY, x | (y << 16));
47 OUTREG32(CMD_2D, RECTANGLE_FILL | CMD_2D_GO | (ROP_COPY << 24));
63 OUTREG32(DST_FORMAT, fmt);
64 OUTREG32(COLOR_BACK, color);
65 OUTREG32(COLOR_FORE, color);
76 OUTREG32(DST_SIZ
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H A D3dfx_overlay.cpp42 OUTREG32(VIDEO_CHROMA_MIN, color);
43 OUTREG32(VIDEO_CHROMA_MAX, color);
76 OUTREG32(VIDEO_PROC_CONFIG, videoConfig);
91 OUTREG32(VIDEO_OVERLAY_START_COORDS, x1 | (y1 << 12));
92 OUTREG32(VIDEO_OVERLAY_END_COORDS, x2 | (y2 << 12));
94 OUTREG32(VIDEO_OVERLAY_DUDX, dudx);
95 OUTREG32(VIDEO_OVERLAY_DUDX_OFFSET_SRC_WIDTH, ((x1 & 0x0001ffff) << 3)
97 OUTREG32(VIDEO_OVERLAY_DVDY, dudy);
98 OUTREG32(VIDEO_OVERLAY_DVDY_OFFSET, (y1 & 0x0000ffff) << 3);
107 OUTREG32(VIDEO_DESKTOP_OVERLAY_STRID
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H A D3dfx_edid.cpp38 OUTREG32(VIDEO_SERIAL_PARALLEL_PORT, reg);
57 OUTREG32(VIDEO_SERIAL_PARALLEL_PORT, reg | VSP_ENABLE_IIC0);
61 OUTREG32(VIDEO_SERIAL_PARALLEL_PORT, reg);
H A D3dfx_cursor.cpp29 OUTREG32(VIDEO_PROC_CONFIG, config);
37 OUTREG32(HW_CURSOR_LOC, ((y + 63) << 16) | (x + 63));
79 OUTREG32(HW_CURSOR_COLOR0, 0xffffff);
80 OUTREG32(HW_CURSOR_COLOR1, 0);
H A D3dfx_mode.cpp125 OUTREG32(CMD_3D, CMD_3D_NOP);
325 OUTREG32(VIDEO_PROC_CONFIG, 0);
326 OUTREG32(PLL_CTRL0, pllFreq);
337 OUTREG32(VGA_INIT0, vgaInit0);
338 OUTREG32(DAC_MODE, dacMode);
339 OUTREG32(VIDEO_DESKTOP_OVERLAY_STRIDE, mode.bytesPerRow);
340 OUTREG32(HW_CURSOR_PAT_ADDR, si.cursorOffset);
341 OUTREG32(VIDEO_SCREEN_SIZE, screenSize);
342 OUTREG32(VIDEO_DESKTOP_START_ADDR, si.frameBufferOffset);
345 OUTREG32(CLIP0_MI
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H A D3dfx_dpms.cpp85 OUTREG32(DAC_MODE, dacMode);
H A D3dfx_init.cpp42 OUTREG32(MISC_INIT1, miscInit1);
H A Daccelerant.h183 #define OUTREG32(addr, val) *((vuint32*)(gInfo.regs + addr)) = val macro
/haiku/src/add-ons/accelerants/intel_810/
H A Di810_mode.cpp210 OUTREG32(MEM_MODE, INREG32(MEM_MODE) | 4);
234 OUTREG32(PIXPIPE_CONFIG, temp32);
242 OUTREG32(FWATER_BLC, temp32);
H A Di810_regs.h117 #define OUTREG32(addr, val) (*((vuint32*)(gInfo.regs + (addr))) = (val)) macro
/haiku/src/add-ons/accelerants/s3/
H A Dregister_io.cpp23 #define OUTREG32(addr, val) *((vuint32*)(gInfo.regs + addr)) = val macro
115 OUTREG32(addr, value);
/haiku/src/add-ons/kernel/drivers/graphics/intel_810/
H A Ddriver.cpp124 #define OUTREG32(addr, val) (*((vuint32*)(di.regs + (addr))) = (val)) macro
322 OUTREG32(PAGE_TABLE_CONTROL, entry.address | PAGE_TABLE_ENABLED);
352 OUTREG32(PTE_BASE + ((offset / B_PAGE_SIZE) * 4),

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