Searched refs:MvddRatio (Results 1 - 4 of 4) sorted by relevance

/linux-master/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu11_driver_if_sienna_cichlid.h883 uint32_t MvddRatio; // This is used for MVDD Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16) member in struct:__anon726
1244 uint32_t MvddRatio; // This is used for MVDD Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16) member in struct:__anon727
H A Dsmu11_driver_if_navi10.h805 uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16) member in struct:__anon671
/linux-master/drivers/gpu/drm/amd/include/
H A Datomfirmware.h2563 uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16) member in struct:atom_smc_dpm_info_v4_5
2734 uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16) member in struct:atom_smc_dpm_info_v4_7
2812 uint32_t MvddRatio; // This is used for MVDD Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16) member in struct:atom_smc_dpm_info_v4_9
/linux-master/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dsienna_cichlid_ppt.c3036 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
3675 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);

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