Searched refs:MII_QS6612_PCR (Results 1 - 4 of 4) sorted by path

/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/ppc/8260_io/
H A Dfcc_enet.c1066 #define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */ macro
1096 { mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL },
1119 { mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr },
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/ppc/8xx_io/
H A Dfec.c1051 #define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */ macro
1079 { mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL },
1102 { mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr },
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/net/
H A Dfec.c983 #define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */ macro
1007 { mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL },
1026 { mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr },
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/net/phy/
H A Dqsemi.c49 #define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */ macro
66 return phy_write(phydev, MII_QS6612_PCR, 0x0dc0);

Completed in 109 milliseconds