Searched refs:MC_REGISTERS_TABLE_92__data_4_value_10__SHIFT (Results 1 - 2 of 2) sorted by path

/linux-master/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_7_1_0_sh_mask.h3462 #define MC_REGISTERS_TABLE_92__data_4_value_10__SHIFT 0x0 macro
H A Dsmu_7_0_1_sh_mask.h3466 #define MC_REGISTERS_TABLE_92__data_4_value_10__SHIFT 0x0 macro

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