Searched refs:MASTER_COMM_CMD_REG (Results 1 - 5 of 5) sorted by relevance

/linux-master/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_dmcu.h41 SR(MASTER_COMM_CMD_REG), \
63 SR(MASTER_COMM_CMD_REG), \
80 SR(MASTER_COMM_CMD_REG), \
116 DMCU_SF(MASTER_COMM_CMD_REG, \
144 DMCU_SF(MASTER_COMM_CMD_REG, \
162 DMCU_SF(MASTER_COMM_CMD_REG, \
218 uint32_t MASTER_COMM_CMD_REG; member in struct:dce_dmcu_registers
H A Ddce_dmcu.c145 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
148 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
271 REG_UPDATE(MASTER_COMM_CMD_REG,
318 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP);
369 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
424 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
507 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
566 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
569 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0,
711 REG_UPDATE(MASTER_COMM_CMD_REG,
[all...]
H A Ddce_abm.h34 SR(MASTER_COMM_CMD_REG), \
136 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
137 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE1, mask_sh), \
138 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE2, mask_sh)
308 uint32_t MASTER_COMM_CMD_REG; member in struct:dce_abm_registers
H A Ddce_abm.c73 REG_UPDATE_2(MASTER_COMM_CMD_REG,
118 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_BL_SET);
210 REG_UPDATE_2(MASTER_COMM_CMD_REG,
H A Ddce_link_encoder.h151 uint32_t MASTER_COMM_CMD_REG; member in struct:dce110_link_enc_registers

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