Searched refs:L1_CACHE_BYTES (Results 1 - 25 of 182) sorted by relevance

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/linux-master/arch/alpha/include/asm/
H A Dcache.h11 # define L1_CACHE_BYTES 64 macro
17 # define L1_CACHE_BYTES 32 macro
21 #define SMP_CACHE_BYTES L1_CACHE_BYTES
/linux-master/arch/hexagon/include/asm/
H A Dcache.h13 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) macro
15 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES
17 #define __cacheline_aligned __aligned(L1_CACHE_BYTES)
18 #define ____cacheline_aligned __aligned(L1_CACHE_BYTES)
/linux-master/arch/microblaze/include/asm/
H A Dcache.h17 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) macro
19 #define SMP_CACHE_BYTES L1_CACHE_BYTES
22 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES
24 #define ARCH_SLAB_MINALIGN L1_CACHE_BYTES
/linux-master/arch/m68k/include/asm/
H A Dcache.h10 #define L1_CACHE_BYTES (1<< L1_CACHE_SHIFT) macro
12 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES
/linux-master/tools/include/linux/
H A Dcache.h6 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) macro
8 #define SMP_CACHE_BYTES L1_CACHE_BYTES
/linux-master/arch/mips/include/asm/mach-tx49xx/
H A Dkmalloc.h5 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES
/linux-master/include/asm-generic/
H A Dcache.h11 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) macro
/linux-master/arch/mips/include/asm/mach-n64/
H A Dkmalloc.h6 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES
/linux-master/arch/sh/mm/
H A Dflush-sh4.c19 v = aligned_start & ~(L1_CACHE_BYTES-1);
20 end = (aligned_start + size + L1_CACHE_BYTES-1)
21 & ~(L1_CACHE_BYTES-1);
22 cnt = (end - v) / L1_CACHE_BYTES;
25 __ocbwb(v); v += L1_CACHE_BYTES;
26 __ocbwb(v); v += L1_CACHE_BYTES;
27 __ocbwb(v); v += L1_CACHE_BYTES;
28 __ocbwb(v); v += L1_CACHE_BYTES;
29 __ocbwb(v); v += L1_CACHE_BYTES;
30 __ocbwb(v); v += L1_CACHE_BYTES;
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H A Dcache-sh2.c23 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
24 end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
25 & ~(L1_CACHE_BYTES-1);
26 for (v = begin; v < end; v+=L1_CACHE_BYTES) {
44 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
45 end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
46 & ~(L1_CACHE_BYTES-1);
48 for (v = begin; v < end; v+=L1_CACHE_BYTES)
75 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
76 end = ((unsigned long)start + size + L1_CACHE_BYTES
[all...]
H A Dcache-sh2a.c57 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
58 end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
59 & ~(L1_CACHE_BYTES-1);
70 for (v = begin; v < end; v += L1_CACHE_BYTES) {
78 for (v = begin; v < end; v += L1_CACHE_BYTES)
97 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
98 end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
99 & ~(L1_CACHE_BYTES-1);
104 for (v = begin; v < end; v+=L1_CACHE_BYTES) {
127 begin = (unsigned long)start & ~(L1_CACHE_BYTES
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/linux-master/arch/arm/include/asm/
H A Dcache.h9 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) macro
18 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES
/linux-master/arch/openrisc/include/asm/
H A Dcache.h24 #define L1_CACHE_BYTES 16 macro
/linux-master/arch/s390/include/asm/
H A Dcache.h13 #define L1_CACHE_BYTES 256 macro
/linux-master/arch/loongarch/include/asm/
H A Dcache.h9 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) macro
/linux-master/arch/nios2/include/asm/
H A Dcache.h19 #define L1_CACHE_BYTES NIOS2_ICACHE_LINE_SIZE macro
21 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES
/linux-master/arch/riscv/include/asm/
H A Dcache.h12 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) macro
15 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES
/linux-master/arch/xtensa/include/asm/
H A Dcache.h17 #define L1_CACHE_BYTES XCHAL_DCACHE_LINESIZE macro
18 #define SMP_CACHE_BYTES L1_CACHE_BYTES
32 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES
/linux-master/arch/csky/mm/
H A Dcachev2.c26 unsigned long i = start & ~(L1_CACHE_BYTES - 1);
28 for (; i < end; i += L1_CACHE_BYTES)
49 unsigned long i = param->start & ~(L1_CACHE_BYTES - 1);
54 for (; i < param->end; i += L1_CACHE_BYTES)
81 unsigned long i = start & ~(L1_CACHE_BYTES - 1);
83 for (; i < end; i += L1_CACHE_BYTES)
97 unsigned long i = start & ~(L1_CACHE_BYTES - 1);
99 for (; i < end; i += L1_CACHE_BYTES)
106 unsigned long i = start & ~(L1_CACHE_BYTES - 1);
108 for (; i < end; i += L1_CACHE_BYTES)
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/linux-master/drivers/md/dm-vdo/
H A Dcpu.h50 unsigned int offset = ((uintptr_t) address % L1_CACHE_BYTES);
51 unsigned int cache_lines = (1 + ((size + offset) / L1_CACHE_BYTES));
55 address += L1_CACHE_BYTES;
/linux-master/arch/um/include/asm/
H A Dcache.h16 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) macro
/linux-master/arch/sparc/include/asm/
H A Dcache.h14 #define L1_CACHE_BYTES 32 macro
/linux-master/arch/sh/include/asm/
H A Dcache.h15 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) macro
21 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES
/linux-master/arch/powerpc/include/asm/
H A Dpage_32.h44 WARN_ON((unsigned long)addr & (L1_CACHE_BYTES - 1));
46 for (i = 0; i < PAGE_SIZE / L1_CACHE_BYTES; i++, addr += L1_CACHE_BYTES)
/linux-master/arch/mips/include/asm/
H A Dcache.h15 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) macro

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