Searched refs:IRQENABLE_L0 (Results 1 - 3 of 3) sorted by relevance
| /linux-master/arch/arm/mach-omap2/ |
| H A D | dma.c | 42 [IRQENABLE_L0] = { 0x0018, 0x00, OMAP_DMA_REG_32BIT },
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| /linux-master/include/linux/ |
| H A D | omap-dma.h | 145 IRQSTATUS_L1, IRQSTATUS_L2, IRQSTATUS_L3, IRQENABLE_L0, enumerator in enum:omap_reg_offsets
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| /linux-master/drivers/dma/ti/ |
| H A D | omap-dma.c | 735 val = omap_dma_glbl_read(od, IRQENABLE_L0);
737 omap_dma_glbl_write(od, IRQENABLE_L0, val);
1571 * We are using IRQENABLE_L1, and legacy DMA code was using IRQENABLE_L0.
1577 od->context.irqenable_l0 = omap_dma_glbl_read(od, IRQENABLE_L0);
1589 omap_dma_glbl_write(od, IRQENABLE_L0, od->context.irqenable_l0);
1864 omap_dma_glbl_write(od, IRQENABLE_L0, 0);
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