Searched refs:INREG (Results 1 - 25 of 35) sorted by relevance

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/haiku/src/add-ons/accelerants/ati/
H A Drage128_init.cpp70 uint32 slots = INREG(R128_GUI_STAT) & R128_GUI_FIFOCNT_MASK;
76 INREG(R128_GUI_STAT) & R128_GUI_FIFOCNT_MASK,
77 INREG(R128_GUI_STAT),
78 INREG(R128_GUI_PROBE));
97 if ( ! (INREG(R128_GUI_STAT) & R128_GUI_ACTIVE)) {
104 INREG(R128_GUI_STAT) & R128_GUI_FIFOCNT_MASK,
105 INREG(R128_GUI_STAT),
106 INREG(R128_GUI_PROBE));
121 si.videoMemSize = INREG(R128_CONFIG_MEMSIZE);
134 switch (INREG(R128_MEM_CNT
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H A Drage128_dpms.cpp35 uint32 tmp = INREG(R128_CRTC_EXT_CNTL);
99 genCtrl = INREG(R128_LVDS_GEN_CNTL);
108 genCtrl = INREG(R128_LVDS_GEN_CNTL);
125 OUTREG(R128_FP_GEN_CNTL, INREG(R128_FP_GEN_CNTL)
132 OUTREG(R128_FP_GEN_CNTL, INREG(R128_FP_GEN_CNTL)
H A Dmach64_init.cpp56 uint32 memCntl = INREG(MEM_CNTL);
72 int memType = INREG(CONFIG_STAT0) & 0x7;
118 uint32 dspConfig = INREG(DSP_CONFIG);
182 uint32 memCntl = INREG(MEM_CNTL);
236 while ((INREG(FIFO_STAT) & 0xffff) > (0x8000ul >> entries)) ;
249 while (INREG(GUI_STAT) & ENGINE_BUSY) ;
H A Drage128_draw.cpp30 if ( ! (INREG(R128_PC_NGUI_CTLSTAT) & R128_PC_BUSY))
43 uint32 clockCntlIndex = INREG(R128_CLOCK_CNTL_INDEX);
48 uint32 genResetCntl = INREG(R128_GEN_RESET_CNTL);
51 INREG(R128_GEN_RESET_CNTL);
53 INREG(R128_GEN_RESET_CNTL);
H A Dmach64_dpms.cpp34 uint32 tmp = INREG(CRTC_GEN_CNTL);
H A Daccelerant.h238 #define INREG(addr) *((vuint32*)(gInfo.regs + addr)) macro
247 (OUTREG(addr, (INREG(addr) & ~(mask)) | ((value) & (mask))))
H A Dmach64_draw.cpp25 uint32 genTestCntl = INREG(GEN_TEST_CNTL) & ~GUI_ENGINE_ENABLE;
31 OUTREG(BUS_CNTL, INREG(BUS_CNTL) | BUS_HOST_ERR_ACK | BUS_FIFO_ERR_ACK);
/haiku/headers/private/graphics/radeon/
H A Dmmio.h18 #define INREG( regs, addr ) (*((vuint32 *)(regs + (addr)))) macro
24 uint32 tmp = INREG( (regs), (addr) ); \
/haiku/src/add-ons/kernel/drivers/graphics/radeon/
H A Dpll_access.c24 INREG( regs, RADEON_CLOCK_CNTL_DATA);
25 INREG( regs, RADEON_CRTC_GEN_CNTL);
50 save = INREG( regs, RADEON_CLOCK_CNTL_INDEX );
53 tmp = INREG( regs, RADEON_CLOCK_CNTL_DATA );
65 res = INREG( regs, RADEON_CLOCK_CNTL_DATA );
H A Dvip.c48 INREG( regs, RADEON_VIPH_REG_DATA );
62 *data = INREG( regs, RADEON_VIPH_REG_DATA );
127 INREG( regs, RADEON_VIPH_TIMEOUT_STAT) &
134 INREG( regs, RADEON_VIPH_REG_DATA);
143 tmp = INREG( regs, RADEON_VIPH_TIMEOUT_STAT);
150 *buffer=(uint8)(INREG( regs, RADEON_VIPH_REG_DATA) & 0xff);
153 *(uint16 *)buffer=(uint16) (INREG( regs, RADEON_VIPH_REG_DATA) & 0xffff);
156 *(uint32 *)buffer=(uint32) ( INREG( regs, RADEON_VIPH_REG_DATA) & 0xffffffff);
166 (INREG( regs, RADEON_VIPH_TIMEOUT_STAT) & 0xffffff00) | RADEON_VIPH_TIMEOUT_STAT_VIPH_REGR_DIS);
311 OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT, (INREG( reg
[all...]
H A DCP_setup.c130 if( (INREG( di->regs, RADEON_RBBM_STATUS ) & RADEON_RBBM_ACTIVE) == 0 ) {
147 INREG( di->regs, RADEON_RBBM_STATUS ),
148 INREG( di->regs, RADEON_CP_STAT ),
149 INREG( di->regs, RADEON_AIC_TLB_ADDR ),
150 INREG( di->regs, RADEON_AIC_TLB_DATA ));
167 int slots = INREG( di->regs, RADEON_RBBM_STATUS ) & RADEON_RBBM_FIFOCNT_MASK;
192 if( (INREG( di->regs, RADEON_RB2D_DSTCACHE_CTLSTAT )
217 clock_cntl_index = INREG( regs, RADEON_CLOCK_CNTL_INDEX );
231 host_path_cntl = INREG( regs, RADEON_HOST_PATH_CNTL );
232 rbbm_soft_reset = INREG( reg
[all...]
H A Dinit.c313 di->dac2_cntl = INREG( di->regs, RADEON_DAC_CNTL2 );
316 si->tmds_pll_cntl = INREG( di->regs, RADEON_TMDS_PLL_CNTL);
317 si->tmds_transmitter_cntl = INREG( di->regs, RADEON_TMDS_TRANSMITTER_CNTL);
323 INREG( di->regs, RADEON_LVDS_GEN_CNTL ));
325 INREG( di->regs, RADEON_LVDS_PLL_CNTL ));
327 INREG( di->regs, RADEON_TMDS_PLL_CNTL ));
329 INREG( di->regs, RADEON_TMDS_TRANSMITTER_CNTL ));
331 INREG( di->regs, RADEON_FP_GEN_CNTL ));
333 INREG( di->regs, RADEON_FP2_GEN_CNTL ));
335 INREG( d
[all...]
H A Dbios.c214 tmp = INREG( di->regs, RADEON_BIOS_4_SCRATCH );
252 tmp = INREG( di->regs, RADEON_FP_GEN_CNTL);
634 ((INREG( regs, RADEON_FP_VERT_STRETCH ) & RADEON_VERT_PANEL_SIZE)
638 (((INREG( regs, RADEON_FP_HORZ_STRETCH ) & RADEON_HORZ_PANEL_SIZE)
654 r = INREG( regs, RADEON_FP_CRTC_H_TOTAL_DISP );
662 r = INREG( regs, RADEON_FP_H_SYNC_STRT_WID );
674 r = INREG( regs, RADEON_FP_CRTC_V_TOTAL_DISP );
681 r = INREG( regs, RADEON_FP_V_SYNC_STRT_WID );
687 r = INREG( regs, RADEON_CRTC_H_TOTAL_DISP );
694 r = INREG( reg
[all...]
H A Dmem_controller.c42 uint32 aper0 = INREG( di->regs, RADEON_CONFIG_APER_0_BASE );
119 tom = INREG( di->regs, RADEON_NB_TOM );
H A Dirq.c110 full_int_status = INREG(regs, RADEON_GEN_INT_STATUS);
111 int_status = full_int_status & INREG(regs, RADEON_GEN_INT_CNTL);
128 cap_status = INREG(regs, RADEON_CAP_INT_STATUS);
129 cap_status &= INREG(regs, RADEON_CAP_INT_CNTL);
H A DDMA.c176 while( (INREG( di->regs, RADEON_DMA_VID_STATUS ) & RADEON_DMA_STATUS_ACTIVE) != 0 ) {
/haiku/src/add-ons/accelerants/radeon/
H A Dflat_panel.c25 values->fp_horz_stretch = INREG( regs, RADEON_FP_HORZ_STRETCH );
26 values->fp_vert_stretch = INREG( regs, RADEON_FP_VERT_STRETCH );
122 values->fp_gen_cntl = INREG( regs, RADEON_FP_GEN_CNTL );
123 values->fp2_gen_cntl = INREG( regs, RADEON_FP2_GEN_CNTL );
124 values->lvds_gen_cntl = INREG( regs, RADEON_LVDS_GEN_CNTL );
125 values->tmds_pll_cntl = INREG( regs, RADEON_TMDS_PLL_CNTL );
126 values->tmds_trans_cntl = INREG( regs, RADEON_TMDS_TRANSMITTER_CNTL );
127 values->fp_h_sync_strt_wid = INREG( regs, RADEON_FP_H_SYNC_STRT_WID );
128 values->fp_v_sync_strt_wid = INREG( regs, RADEON_FP_V_SYNC_STRT_WID );
129 values->fp2_h_sync_strt_wid = INREG( reg
[all...]
H A Dmonitor_detection.c43 value = INREG(regs, info->port);
59 value = INREG(regs, info->port);
109 old_crtc_ext_cntl = INREG(regs, RADEON_CRTC_EXT_CNTL);
116 old_dac_ext_cntl = INREG(regs, RADEON_DAC_EXT_CNTL);
124 old_dac_cntl = INREG(regs, RADEON_DAC_CNTL);
137 found = (INREG(regs, RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT) != 0;
185 old_crtc2_gen_cntl = INREG(regs, RADEON_CRTC2_GEN_CNTL);
192 old_tv_dac_cntl = INREG(regs, RADEON_TV_DAC_CNTL);
204 old_dac_cntl2 = INREG(regs, RADEON_DAC_CNTL2);
214 found = (INREG(reg
[all...]
H A DSetDisplayMode.c283 SHOW_FLOW( 0, "RADEON_DAC_CNTL %08X ", INREG( regs, RADEON_DAC_CNTL ));
284 SHOW_FLOW( 0, "RADEON_DAC_CNTL2 %08X ", INREG( regs, RADEON_DAC_CNTL2 ));
285 SHOW_FLOW( 0, "RADEON_TV_DAC_CNTL %08X ", INREG( regs, RADEON_TV_DAC_CNTL ));
286 SHOW_FLOW( 0, "RADEON_DISP_OUTPUT_CNTL %08X ", INREG( regs, RADEON_DISP_OUTPUT_CNTL ));
287 SHOW_FLOW( 0, "RADEON_AUX_SC_CNTL %08X ", INREG( regs, RADEON_AUX_SC_CNTL ));
288 SHOW_FLOW( 0, "RADEON_CRTC_EXT_CNTL %08X ", INREG( regs, RADEON_CRTC_EXT_CNTL ));
289 SHOW_FLOW( 0, "RADEON_CRTC_GEN_CNTL %08X ", INREG( regs, RADEON_CRTC_GEN_CNTL ));
290 SHOW_FLOW( 0, "RADEON_CRTC2_GEN_CNTL %08X ", INREG( regs, RADEON_CRTC2_GEN_CNTL ));
291 SHOW_FLOW( 0, "RADEON_DISP_MISC_CNTL %08X ", INREG( regs, RADEON_DISP_MISC_CNTL ));
292 SHOW_FLOW( 0, "RADEON_FP_GEN_CNTL %08X ", INREG( reg
[all...]
H A Dmonitor_routing.c31 values->dac_cntl = INREG( regs, RADEON_DAC_CNTL );
32 values->dac_cntl2 = INREG( regs, RADEON_DAC_CNTL2 );
33 values->crtc_ext_cntl = INREG( regs, RADEON_CRTC_EXT_CNTL );
34 values->crtc2_gen_cntl = INREG( regs, RADEON_CRTC2_GEN_CNTL );
35 values->disp_output_cntl = INREG( regs, RADEON_DISP_OUTPUT_CNTL );
47 values->disp_hw_debug = INREG( regs, RADEON_DISP_HW_DEBUG );
51 values->disp_tv_out_cntl = INREG( regs, RADEON_DISP_TV_OUT_CNTL );
59 values->gpiopad_a = INREG( regs, RADEON_GPIOPAD_A );
68 values->tv_dac_cntl = INREG( regs, RADEON_TV_DAC_CNTL );
72 values->tv_master_cntl = INREG( reg
[all...]
H A Dinternal_tv_out.c142 status = INREG( regs, RADEON_TV_HOST_RD_WT_CNTL );
149 res = INREG( regs, RADEON_TV_HOST_READ_DATA );
176 status = INREG( regs, RADEON_TV_HOST_RD_WT_CNTL );
237 INREG( regs, mapping->address );
H A Ddriver_wrapper.c34 int slots = INREG( ai->regs, RADEON_RBBM_STATUS ) & RADEON_RBBM_FIFOCNT_MASK;
H A Ddpms.c345 tmp = INREG( di->regs, RADEON_CRTC_EXT_CNTL );
365 tmp = INREG( di->regs, RADEON_CRTC2_GEN_CNTL );
H A DCursor.c227 tmp = INREG( ai->regs, RADEON_CRTC_GEN_CNTL );
238 tmp = INREG( ai->regs, RADEON_CRTC2_GEN_CNTL );
/haiku/src/add-ons/accelerants/intel_810/
H A Di810_regs.h122 (OUTREG(addr, (INREG(addr) & ~mask) | (value & mask)))

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