/linux-master/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/ |
H A D | hmem_private.h | 24 const hmem_ID_t ID) 26 assert(ID < N_HMEM_ID); 27 (void)ID; 23 sizeof_hmem( const hmem_ID_t ID) argument
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H A D | sp.c | 25 const sp_ID_t ID, 29 sp_ctrl_setbit(ID, SP_IRQ_READY_REG, SP_IRQ_READY_BIT); 31 sp_ctrl_setbit(ID, SP_IRQ_CLEAR_REG, SP_IRQ_CLEAR_BIT); 33 sp_ctrl_clearbit(ID, SP_IRQ_READY_REG, SP_IRQ_READY_BIT); 24 cnd_sp_irq_enable( const sp_ID_t ID, const bool cnd) argument
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H A D | gpio_private.h | 26 const gpio_ID_t ID, 30 OP___assert(ID < N_GPIO_ID); 31 OP___assert(GPIO_BASE[ID] != (hrt_address) - 1); 32 ia_css_device_store_uint32(GPIO_BASE[ID] + reg * sizeof(hrt_data), value); 37 const gpio_ID_t ID, 40 OP___assert(ID < N_GPIO_ID); 41 OP___assert(GPIO_BASE[ID] != (hrt_address) - 1); 42 return ia_css_device_load_uint32(GPIO_BASE[ID] + reg * sizeof(hrt_data)); 25 gpio_reg_store( const gpio_ID_t ID, const unsigned int reg, const hrt_data value) argument
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H A D | dma_private.h | 25 STORAGE_CLASS_DMA_C void dma_reg_store(const dma_ID_t ID, argument 29 assert(ID < N_DMA_ID); 30 assert(DMA_BASE[ID] != (hrt_address) - 1); 31 ia_css_device_store_uint32(DMA_BASE[ID] + reg * sizeof(hrt_data), value); 34 STORAGE_CLASS_DMA_C hrt_data dma_reg_load(const dma_ID_t ID, 37 assert(ID < N_DMA_ID); 38 assert(DMA_BASE[ID] != (hrt_address) - 1); 39 return ia_css_device_load_uint32(DMA_BASE[ID] + reg * sizeof(hrt_data));
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H A D | irq_private.h | 26 const irq_ID_t ID, 30 assert(ID < N_IRQ_ID); 31 assert(IRQ_BASE[ID] != (hrt_address) - 1); 32 ia_css_device_store_uint32(IRQ_BASE[ID] + reg * sizeof(hrt_data), value); 37 const irq_ID_t ID, 40 assert(ID < N_IRQ_ID); 41 assert(IRQ_BASE[ID] != (hrt_address) - 1); 42 return ia_css_device_load_uint32(IRQ_BASE[ID] + reg * sizeof(hrt_data)); 25 irq_reg_store( const irq_ID_t ID, const unsigned int reg, const hrt_data value) argument
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H A D | mmu.c | 20 const mmu_ID_t ID, 23 mmu_reg_store(ID, _HRT_MMU_PAGE_TABLE_BASE_ADDRESS_REG_IDX, base_index); 28 const mmu_ID_t ID) 30 return mmu_reg_load(ID, _HRT_MMU_PAGE_TABLE_BASE_ADDRESS_REG_IDX); 34 const mmu_ID_t ID) 36 mmu_reg_store(ID, _HRT_MMU_INVALIDATE_TLB_REG_IDX, 1); 19 mmu_set_page_table_base_index( const mmu_ID_t ID, const hrt_data base_index) argument 27 mmu_get_page_table_base_index( const mmu_ID_t ID) argument 33 mmu_invalidate_cache( const mmu_ID_t ID) argument
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H A D | isp.c | 28 const isp_ID_t ID, 32 isp_ctrl_setbit(ID, ISP_IRQ_READY_REG, ISP_IRQ_READY_BIT); 34 isp_ctrl_setbit(ID, ISP_IRQ_CLEAR_REG, ISP_IRQ_CLEAR_BIT); 36 isp_ctrl_clearbit(ID, ISP_IRQ_READY_REG, 44 /* Inspect readiness of an ISP indexed by ID */ 45 unsigned int isp_is_ready(isp_ID_t ID) argument 47 assert(ID < N_ISP_ID); 48 return isp_ctrl_getbit(ID, ISP_SC_REG, ISP_IDLE_BIT); 51 /* Inspect sleeping of an ISP indexed by ID */ 52 unsigned int isp_is_sleeping(isp_ID_t ID) argument 27 cnd_isp_irq_enable( const isp_ID_t ID, const bool cnd) argument 59 isp_start(isp_ID_t ID) argument 65 isp_wake(isp_ID_t ID) argument [all...] |
H A D | gp_device.c | 24 const gp_device_ID_t ID, 27 assert(ID < N_GP_DEVICE_ID); 30 state->syncgen_enable = gp_device_reg_load(ID, 32 state->syncgen_free_running = gp_device_reg_load(ID, 34 state->syncgen_pause = gp_device_reg_load(ID, 36 state->nr_frames = gp_device_reg_load(ID, 38 state->syngen_nr_pix = gp_device_reg_load(ID, 40 state->syngen_nr_pix = gp_device_reg_load(ID, 42 state->syngen_nr_lines = gp_device_reg_load(ID, 44 state->syngen_hblank_cycles = gp_device_reg_load(ID, 23 gp_device_get_state( const gp_device_ID_t ID, gp_device_state_t *state) argument [all...] |
H A D | irq.c | 25 const irq_ID_t ID); 28 const irq_ID_t ID); 60 const irq_ID_t ID) 64 assert(ID < N_IRQ_ID); 65 assert(IRQ_N_CHANNEL[ID] <= HRT_DATA_WIDTH); 67 if (IRQ_N_CHANNEL[ID] < HRT_DATA_WIDTH) { 68 mask = ~((~(hrt_data)0) >> IRQ_N_CHANNEL[ID]); 71 irq_reg_store(ID, 80 const irq_ID_t ID, 83 unsigned int mask = irq_reg_load(ID, 59 irq_clear_all( const irq_ID_t ID) argument 79 irq_enable_channel( const irq_ID_t ID, const unsigned int irq_id) argument 121 irq_enable_pulse( const irq_ID_t ID, bool pulse) argument 136 irq_disable_channel( const irq_ID_t ID, const unsigned int irq_id) argument 167 irq_get_channel_id( const irq_ID_t ID, unsigned int *irq_id) argument 207 irq_raise( const irq_ID_t ID, const irq_sw_channel_id_t irq_id) argument 242 irq_ID_t ID = virq_get_irq_id(irq_ID, &channel_ID); local 281 irq_ID_t ID; local 309 irq_ID_t ID; local 326 irq_ID_t ID; local 389 irq_wait_for_write_complete( const irq_ID_t ID) argument 398 any_irq_channel_enabled( const irq_ID_t ID) argument 415 irq_ID_t ID; local [all...] |
H A D | isp_private.h | 31 const isp_ID_t ID, 35 assert(ID < N_ISP_ID); 36 assert(ISP_CTRL_BASE[ID] != (hrt_address) - 1); 38 ia_css_device_store_uint32(ISP_CTRL_BASE[ID] + reg * sizeof(hrt_data), value); 40 hrt_master_port_store_32(ISP_CTRL_BASE[ID] + reg * sizeof(hrt_data), value); 46 const isp_ID_t ID, 49 assert(ID < N_ISP_ID); 50 assert(ISP_CTRL_BASE[ID] != (hrt_address) - 1); 52 return ia_css_device_load_uint32(ISP_CTRL_BASE[ID] + reg * sizeof(hrt_data)); 54 return hrt_master_port_uload_32(ISP_CTRL_BASE[ID] 30 isp_ctrl_store( const isp_ID_t ID, const unsigned int reg, const hrt_data value) argument [all...] |
H A D | event_fifo_private.h | 27 STORAGE_CLASS_EVENT_C void event_wait_for(const event_ID_t ID) argument 29 assert(ID < N_EVENT_ID); 30 assert(event_source_addr[ID] != ((hrt_address) - 1)); 31 (void)ia_css_device_load_uint32(event_source_addr[ID]); 35 STORAGE_CLASS_EVENT_C void cnd_event_wait_for(const event_ID_t ID, 39 event_wait_for(ID); 43 STORAGE_CLASS_EVENT_C hrt_data event_receive_token(const event_ID_t ID) 45 assert(ID < N_EVENT_ID); 46 assert(event_source_addr[ID] != ((hrt_address) - 1)); 47 return ia_css_device_load_uint32(event_source_addr[ID]); [all...] |
H A D | sp_private.h | 26 const sp_ID_t ID, 30 assert(ID < N_SP_ID); 31 assert(SP_CTRL_BASE[ID] != (hrt_address)-1); 32 ia_css_device_store_uint32(SP_CTRL_BASE[ID] + reg * sizeof(hrt_data), value); 37 const sp_ID_t ID, 40 assert(ID < N_SP_ID); 41 assert(SP_CTRL_BASE[ID] != (hrt_address)-1); 42 return ia_css_device_load_uint32(SP_CTRL_BASE[ID] + reg * sizeof(hrt_data)); 46 const sp_ID_t ID, 50 hrt_data val = sp_ctrl_load(ID, re 25 sp_ctrl_store( const sp_ID_t ID, const hrt_address reg, const hrt_data value) argument [all...] |
H A D | input_formatter_private.h | 26 const input_formatter_ID_t ID, 30 assert(ID < N_INPUT_FORMATTER_ID); 31 assert(INPUT_FORMATTER_BASE[ID] != (hrt_address)-1); 33 ia_css_device_store_uint32(INPUT_FORMATTER_BASE[ID] + reg_addr, value); 38 const input_formatter_ID_t ID, 41 assert(ID < N_INPUT_FORMATTER_ID); 42 assert(INPUT_FORMATTER_BASE[ID] != (hrt_address)-1); 44 return ia_css_device_load_uint32(INPUT_FORMATTER_BASE[ID] + reg_addr); 25 input_formatter_reg_store( const input_formatter_ID_t ID, const hrt_address reg_addr, const hrt_data value) argument
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H A D | gp_device_private.h | 26 const gp_device_ID_t ID, 30 assert(ID < N_GP_DEVICE_ID); 31 assert(GP_DEVICE_BASE[ID] != (hrt_address) - 1); 33 ia_css_device_store_uint32(GP_DEVICE_BASE[ID] + reg_addr, value); 38 const gp_device_ID_t ID, 41 assert(ID < N_GP_DEVICE_ID); 42 assert(GP_DEVICE_BASE[ID] != (hrt_address)-1); 44 return ia_css_device_load_uint32(GP_DEVICE_BASE[ID] + reg_addr); 25 gp_device_reg_store( const gp_device_ID_t ID, const unsigned int reg_addr, const hrt_data value) argument
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H A D | fifo_monitor_private.h | 33 const fifo_monitor_ID_t ID, 37 assert(ID == FIFO_MONITOR0_ID); 38 assert(FIFO_MONITOR_BASE[ID] != (hrt_address) - 1); 40 (void)ID; 48 const fifo_monitor_ID_t ID, 51 assert(ID == FIFO_MONITOR0_ID); 52 assert(FIFO_MONITOR_BASE[ID] != (hrt_address) - 1); 54 (void)ID; 60 const fifo_monitor_ID_t ID, 64 assert(ID < N_FIFO_MONITOR_I 32 fifo_switch_set( const fifo_monitor_ID_t ID, const fifo_switch_t switch_id, const hrt_data sel) argument [all...] |
H A D | timed_ctrl_private.h | 26 const timed_ctrl_ID_t ID, 30 OP___assert(ID < N_TIMED_CTRL_ID); 31 OP___assert(TIMED_CTRL_BASE[ID] != (hrt_address) - 1); 32 ia_css_device_store_uint32(TIMED_CTRL_BASE[ID] + reg * sizeof(hrt_data), value); 25 timed_ctrl_reg_store( const timed_ctrl_ID_t ID, const unsigned int reg, const hrt_data value) argument
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/linux-master/drivers/staging/media/atomisp/pci/css_2401_system/host/ |
H A D | pixelgen_private.h | 33 const pixelgen_ID_t ID, 36 assert(ID < N_PIXELGEN_ID); 37 assert(PIXELGEN_CTRL_BASE[ID] != (hrt_address) - 1); 38 return ia_css_device_load_uint32(PIXELGEN_CTRL_BASE[ID] + reg * sizeof( 47 const pixelgen_ID_t ID, 51 assert(ID < N_PIXELGEN_ID); 52 assert(PIXELGEN_CTRL_BASE[ID] != (hrt_address)-1); 54 ia_css_device_store_uint32(PIXELGEN_CTRL_BASE[ID] + reg * sizeof(hrt_data), 70 const pixelgen_ID_t ID, 74 pixelgen_ctrl_reg_load(ID, _PXG_COM_ENABLE_REG_ID 32 pixelgen_ctrl_reg_load( const pixelgen_ID_t ID, const hrt_address reg) argument [all...] |
H A D | csi_rx_private.h | 38 const csi_rx_frontend_ID_t ID, 41 assert(ID < N_CSI_RX_FRONTEND_ID); 42 assert(CSI_RX_FE_CTRL_BASE[ID] != (hrt_address)-1); 43 return ia_css_device_load_uint32(CSI_RX_FE_CTRL_BASE[ID] + reg * sizeof( 52 const csi_rx_frontend_ID_t ID, 56 assert(ID < N_CSI_RX_FRONTEND_ID); 57 assert(CSI_RX_FE_CTRL_BASE[ID] != (hrt_address)-1); 59 ia_css_device_store_uint32(CSI_RX_FE_CTRL_BASE[ID] + reg * sizeof(hrt_data), 68 const csi_rx_backend_ID_t ID, 71 assert(ID < N_CSI_RX_BACKEND_I 37 csi_rx_fe_ctrl_reg_load( const csi_rx_frontend_ID_t ID, const hrt_address reg) argument [all...] |
/linux-master/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/ |
H A D | mmu_public.h | 23 /*! Set the page table base index of MMU[ID] 25 \param ID[in] MMU identifier 28 \return none, MMU[ID].page_table_base_index = base_index 31 const mmu_ID_t ID, 34 /*! Get the page table base index of MMU[ID] 36 \param ID[in] MMU identifier 39 \return MMU[ID].page_table_base_index 42 const mmu_ID_t ID); 44 /*! Invalidate the page table cache of MMU[ID] 46 \param ID[i 67 mmu_reg_store( const mmu_ID_t ID, const unsigned int reg, const hrt_data value) argument [all...] |
H A D | gp_timer_public.h | 22 param ID timer_id 25 gp_timer_init(gp_timer_ID_t ID); 28 param ID timer_id 32 gp_timer_read(gp_timer_ID_t ID);
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H A D | event_fifo_public.h | 22 /*! Blocking read from an event source EVENT[ID] 24 \param ID[in] EVENT identifier 26 \return none, dequeue(event_queue[ID]) 29 const event_ID_t ID); 31 /*! Conditional blocking wait for an event source EVENT[ID] 33 \param ID[in] EVENT identifier 36 \return none, if(cnd) dequeue(event_queue[ID]) 39 const event_ID_t ID, 42 /*! Blocking read from an event source EVENT[ID] 44 \param ID[i [all...] |
H A D | csi_rx_public.h | 28 * @param[in] id The global unique ID of the csi rx fe controller. 32 const csi_rx_frontend_ID_t ID, 38 * @param[in] id The global unique ID of the csi rx fe controller. 42 const csi_rx_frontend_ID_t ID, 48 * @param[in] id The global unique ID of the input-buffer controller. 49 * @param[in] lane The lane ID. 53 const csi_rx_frontend_ID_t ID, 60 * @param[in] id The global unique ID of the csi rx be controller. 64 const csi_rx_backend_ID_t ID, 70 * @param[in] id The global unique ID o [all...] |
H A D | input_formatter_public.h | 22 /*! Reset INPUT_FORMATTER[ID] 24 \param ID[in] INPUT_FORMATTER identifier 26 \return none, reset(INPUT_FORMATTER[ID]) 29 const input_formatter_ID_t ID); 31 /*! Set the blocking mode of INPUT_FORMATTER[ID] 33 \param ID[in] INPUT_FORMATTER identifier 43 \return none, INPUT_FORMATTER[ID].blocking_mode = enable 46 const input_formatter_ID_t ID, 49 /*! Return the data alignment of INPUT_FORMATTER[ID] 51 \param ID[i [all...] |
/linux-master/drivers/staging/media/atomisp/pci/ |
H A D | isp2400_input_system_private.h | 26 const input_system_ID_t ID, 30 assert(ID < N_INPUT_SYSTEM_ID); 31 assert(INPUT_SYSTEM_BASE[ID] != (hrt_address)-1); 32 ia_css_device_store_uint32(INPUT_SYSTEM_BASE[ID] + reg * sizeof(hrt_data), 38 const input_system_ID_t ID, 41 assert(ID < N_INPUT_SYSTEM_ID); 42 assert(INPUT_SYSTEM_BASE[ID] != (hrt_address)-1); 43 return ia_css_device_load_uint32(INPUT_SYSTEM_BASE[ID] + reg * sizeof( 48 const rx_ID_t ID, 52 assert(ID < N_RX_I 25 input_system_reg_store( const input_system_ID_t ID, const hrt_address reg, const hrt_data value) argument [all...] |
H A D | isp2401_input_system_private.h | 27 static inline hrt_data ibuf_ctrl_reg_load(const ibuf_ctrl_ID_t ID, argument 30 assert(ID < N_IBUF_CTRL_ID); 31 assert(IBUF_CTRL_BASE[ID] != (hrt_address)-1); 32 return ia_css_device_load_uint32(IBUF_CTRL_BASE[ID] + reg * sizeof(hrt_data)); 36 static inline void ibuf_ctrl_reg_store(const ibuf_ctrl_ID_t ID, 40 assert(ID < N_IBUF_CTRL_ID); 41 assert(IBUF_CTRL_BASE[ID] != (hrt_address)-1); 43 ia_css_device_store_uint32(IBUF_CTRL_BASE[ID] + reg * sizeof(hrt_data), value); 47 static inline void ibuf_ctrl_get_proc_state(const ibuf_ctrl_ID_t ID, 57 ibuf_ctrl_reg_load(ID, reg_bank_offse [all...] |