Searched refs:ICC (Results 1 - 6 of 6) sorted by relevance

/linux-master/drivers/net/wireless/ath/wil6210/
H A Dinterrupt.c193 wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, ICC),
195 wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, ICC),
197 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICC),
199 wil_w(wil, RGF_INT_GEN_TX_ICR + offsetof(struct RGF_ICR, ICC),
201 wil_w(wil, RGF_INT_GEN_RX_ICR + offsetof(struct RGF_ICR, ICC),
834 /* can't use wil_ioread32_and_clear because ICC value is not set yet */
H A Dwil6210.h169 u32 ICC; /* Cause Control, RW: 0 - W1C, 1 - COR */ member in struct:RGF_ICR
170 u32 ICR; /* Cause, W1C/COR depending on ICC */
171 u32 ICM; /* Cause masked (ICR & ~IMV), W1C/COR depending on ICC */
H A Ddebugfs.c488 {"ICC", 0644, offsetof(struct RGF_ICR, ICC), doff_io32},
/linux-master/drivers/ata/
H A Dsata_fsl.c116 ICC = 0x38, enumerator in enum:__anon48
310 iowrite32((count << 24 | ticks), hcr_base + ICC);
318 dev_dbg(host->dev, "ICC register status: (hcr base: 0x%p) = 0x%x\n",
319 hcr_base, ioread32(hcr_base + ICC));
1343 dev_dbg(host->dev, "icc = 0x%x\n", ioread32(hcr_base + ICC));
1344 iowrite32(0x01000000, hcr_base + ICC);
/linux-master/arch/sparc/kernel/
H A Dentry.S710 and %g1, 0xf, %g1 ! only ICC bits in %psr
724 andn %l0, %l5, %l0 ! clear ICC bits in %psr
725 and %l4, %l5, %l4 ! clear non-ICC bits in user value
/linux-master/drivers/atm/
H A Dnicstar.h440 ICC = 0x30, /* Invalid Cell Count R/clear */ enumerator in enum:ns_regs

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