Searched refs:GRPH_INT_CONTROL (Results 1 - 7 of 7) sorted by relevance

/linux-master/drivers/gpu/drm/radeon/
H A Dcik.c6893 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
6894 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
6897 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
6898 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
6901 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
6902 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
7245 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET,
7247 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET,
7251 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET,
7253 WREG32(GRPH_INT_CONTROL
[all...]
H A Dsid.h864 #define GRPH_INT_CONTROL 0x685c macro
H A Dcikd.h937 #define GRPH_INT_CONTROL 0x685c macro
H A Devergreend.h1329 #define GRPH_INT_CONTROL 0x685c macro
H A Dsi.c5947 WREG32(GRPH_INT_CONTROL + crtc_offsets[i], 0);
6105 WREG32(GRPH_INT_CONTROL + crtc_offsets[i], GRPH_PFLIP_INT_MASK);
H A Devergreen.c4478 WREG32(GRPH_INT_CONTROL + crtc_offsets[i], 0);
4583 WREG32(GRPH_INT_CONTROL + crtc_offsets[i], GRPH_PFLIP_INT_MASK);
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dsid.h867 #define GRPH_INT_CONTROL 0x1A17 macro

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