Searched refs:GIU_IRQ (Results 1 - 15 of 15) sorted by path

/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/char/
H A Dvr41xx_giu.c193 return GIU_IRQ(i);
198 return GIU_IRQ(i + GIUINT_HIGH_OFFSET);
238 set_irq_chip_and_handler(GIU_IRQ(pin),
244 set_irq_chip_and_handler(GIU_IRQ(pin),
273 set_irq_chip_and_handler(GIU_IRQ(pin),
279 set_irq_chip_and_handler(GIU_IRQ(pin),
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-mips/vr41xx/
H A Dcapcella.h36 #define RTL8139_1_IRQ GIU_IRQ(PC104PLUS_INTC_PIN)
37 #define RTL8139_2_IRQ GIU_IRQ(PC104PLUS_INTD_PIN)
38 #define PC104PLUS_INTA_IRQ GIU_IRQ(PC104PLUS_INTA_PIN)
39 #define PC104PLUS_INTB_IRQ GIU_IRQ(PC104PLUS_INTB_PIN)
40 #define PC104PLUS_INTC_IRQ GIU_IRQ(PC104PLUS_INTC_PIN)
41 #define PC104PLUS_INTD_IRQ GIU_IRQ(PC104PLUS_INTD_PIN)
H A Dcmbvr4133.h32 #define CMBVR41XX_INTA_IRQ GIU_IRQ(CMBVR41XX_INTA_PIN)
33 #define CMBVR41XX_INTB_IRQ GIU_IRQ(CMBVR41XX_INTB_PIN)
34 #define CMBVR41XX_INTC_IRQ GIU_IRQ(CMBVR41XX_INTC_PIN)
35 #define CMBVR41XX_INTD_IRQ GIU_IRQ(CMBVR41XX_INTD_PIN)
36 #define CMBVR41XX_INTE_IRQ GIU_IRQ(CMBVR41XX_INTE_PIN)
H A Dirq.h78 #define GIU_IRQ(x) (GIU_IRQ_BASE + (x)) /* IRQ 40-71 */ macro
79 #define GIU_IRQ_LAST GIU_IRQ(31)
H A Dmpc30x.h34 #define VRC4173_CASCADE_IRQ GIU_IRQ(VRC4173_PIN)
35 #define MQ200_IRQ GIU_IRQ(MQ200_PIN)
H A Dtb0219.h38 #define TB0219_PCI_SLOT1_IRQ GIU_IRQ(TB0219_PCI_SLOT1_PIN)
39 #define TB0219_PCI_SLOT2_IRQ GIU_IRQ(TB0219_PCI_SLOT2_PIN)
40 #define TB0219_PCI_SLOT3_IRQ GIU_IRQ(TB0219_PCI_SLOT3_PIN)
H A Dtb0226.h37 #define GD82559_1_IRQ GIU_IRQ(GD82559_1_PIN)
38 #define GD82559_2_IRQ GIU_IRQ(GD82559_2_PIN)
39 #define UPD720100_INTA_IRQ GIU_IRQ(UPD720100_INTA_PIN)
40 #define UPD720100_INTB_IRQ GIU_IRQ(UPD720100_INTB_PIN)
41 #define UPD720100_INTC_IRQ GIU_IRQ(UPD720100_INTC_PIN)
H A Dtb0287.h38 #define TB0287_PCI_SLOT_IRQ GIU_IRQ(TB0287_PCI_SLOT_PIN)
39 #define TB0287_SM501_IRQ GIU_IRQ(TB0287_SM501_PIN)
40 #define TB0287_SIL680A_IRQ GIU_IRQ(TB0287_SIL680A_PIN)
41 #define TB0287_RTL8110_IRQ GIU_IRQ(TB0287_RTL8110_PIN)
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm/vr41xx/
H A Dcapcella.h36 #define RTL8139_1_IRQ GIU_IRQ(PC104PLUS_INTC_PIN)
37 #define RTL8139_2_IRQ GIU_IRQ(PC104PLUS_INTD_PIN)
38 #define PC104PLUS_INTA_IRQ GIU_IRQ(PC104PLUS_INTA_PIN)
39 #define PC104PLUS_INTB_IRQ GIU_IRQ(PC104PLUS_INTB_PIN)
40 #define PC104PLUS_INTC_IRQ GIU_IRQ(PC104PLUS_INTC_PIN)
41 #define PC104PLUS_INTD_IRQ GIU_IRQ(PC104PLUS_INTD_PIN)
H A Dcmbvr4133.h32 #define CMBVR41XX_INTA_IRQ GIU_IRQ(CMBVR41XX_INTA_PIN)
33 #define CMBVR41XX_INTB_IRQ GIU_IRQ(CMBVR41XX_INTB_PIN)
34 #define CMBVR41XX_INTC_IRQ GIU_IRQ(CMBVR41XX_INTC_PIN)
35 #define CMBVR41XX_INTD_IRQ GIU_IRQ(CMBVR41XX_INTD_PIN)
36 #define CMBVR41XX_INTE_IRQ GIU_IRQ(CMBVR41XX_INTE_PIN)
H A Dirq.h78 #define GIU_IRQ(x) (GIU_IRQ_BASE + (x)) /* IRQ 40-71 */ macro
79 #define GIU_IRQ_LAST GIU_IRQ(31)
H A Dmpc30x.h34 #define VRC4173_CASCADE_IRQ GIU_IRQ(VRC4173_PIN)
35 #define MQ200_IRQ GIU_IRQ(MQ200_PIN)
H A Dtb0219.h38 #define TB0219_PCI_SLOT1_IRQ GIU_IRQ(TB0219_PCI_SLOT1_PIN)
39 #define TB0219_PCI_SLOT2_IRQ GIU_IRQ(TB0219_PCI_SLOT2_PIN)
40 #define TB0219_PCI_SLOT3_IRQ GIU_IRQ(TB0219_PCI_SLOT3_PIN)
H A Dtb0226.h37 #define GD82559_1_IRQ GIU_IRQ(GD82559_1_PIN)
38 #define GD82559_2_IRQ GIU_IRQ(GD82559_2_PIN)
39 #define UPD720100_INTA_IRQ GIU_IRQ(UPD720100_INTA_PIN)
40 #define UPD720100_INTB_IRQ GIU_IRQ(UPD720100_INTB_PIN)
41 #define UPD720100_INTC_IRQ GIU_IRQ(UPD720100_INTC_PIN)
H A Dtb0287.h38 #define TB0287_PCI_SLOT_IRQ GIU_IRQ(TB0287_PCI_SLOT_PIN)
39 #define TB0287_SM501_IRQ GIU_IRQ(TB0287_SM501_PIN)
40 #define TB0287_SIL680A_IRQ GIU_IRQ(TB0287_SIL680A_PIN)
41 #define TB0287_RTL8110_IRQ GIU_IRQ(TB0287_RTL8110_PIN)

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