Searched refs:GEN8_MASTER_IRQ (Results 1 - 5 of 5) sorted by relevance

/linux-master/drivers/gpu/drm/i915/
H A Di915_irq.c354 master_ctl = intel_uncore_read(&dev_priv->uncore, GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
366 * ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
367 * (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
375 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, 0);
400 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
495 raw_reg_write(regs, GEN8_MASTER_IRQ, 0);
503 return raw_reg_read(regs, GEN8_MASTER_IRQ);
508 raw_reg_write(regs, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
762 intel_uncore_write(uncore, GEN8_MASTER_IRQ, 0);
763 intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ);
[all...]
H A Dintel_gvt_mmio_table.c774 MMIO_D(GEN8_MASTER_IRQ);
H A Di915_reg.h3181 #define GEN8_MASTER_IRQ _MMIO(0x44200)
4281 #define GEN8_MASTER_IRQ macro
/linux-master/drivers/gpu/drm/i915/gvt/
H A Dinterrupt.c236 * GEN8_MASTER_IRQ is a special irq register,
513 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(master, GEN8_MASTER_IRQ);
527 if (!(vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) &
544 if (vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ))
H A Dhandlers.c2497 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,

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