Searched refs:DCLK (Results 1 - 16 of 16) sorted by relevance
| /linux-master/drivers/gpu/drm/i915/gt/ |
| H A D | intel_llc.c | 62 intel_uncore_read(llc_to_gt(llc)->uncore, DCLK) & 0xf;
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| /linux-master/drivers/gpu/drm/amd/pm/powerplay/inc/ |
| H A D | power_state.h | 145 uint32_t DCLK; member in struct:PP_UVD_CLOCKS
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| /linux-master/drivers/gpu/drm/i915/ |
| H A D | intel_mchbar_regs.h | 239 #define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04) macro
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| /linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | processpptables.c | 759 ps->uvd_clocks.DCLK = le32_to_cpu(pnon_clock_info->ulDCLK);
762 ps->uvd_clocks.DCLK = 0;
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| H A D | smu10_hwmgr.c | 934 smu10_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK;
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| H A D | smu8_hwmgr.c | 1428 smu8_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK;
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| H A D | smu7_hwmgr.c | 3636 power_state->uvd_clocks.DCLK = 0;
3729 ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3877 ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
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| H A D | vega10_hwmgr.c | 2060 "Failed to get DCLK clock settings from VBIOS!",
3166 power_state->uvd_clocks.DCLK = 0;
3246 vega10_ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
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| /linux-master/drivers/gpu/drm/amd/pm/swsmu/smu12/ |
| H A D | renoir_ppt.c | 122 CLK_MAP(DCLK, CLOCK_DCLK),
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| /linux-master/drivers/gpu/drm/amd/pm/swsmu/smu13/ |
| H A D | aldebaran_ppt.c | 164 CLK_MAP(DCLK, PPCLK_DCLK),
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| H A D | smu_v13_0_7_ppt.c | 155 CLK_MAP(DCLK, PPCLK_DCLK_0),
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| H A D | smu_v13_0_0_ppt.c | 184 CLK_MAP(DCLK, PPCLK_DCLK_0),
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| H A D | smu_v13_0_6_ppt.c | 184 CLK_MAP(DCLK, PPCLK_DCLK),
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| /linux-master/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| H A D | arcturus_ppt.c | 171 CLK_MAP(DCLK, PPCLK_DCLK),
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| H A D | navi10_ppt.c | 156 CLK_MAP(DCLK, PPCLK_DCLK),
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| H A D | sienna_cichlid_ppt.c | 171 CLK_MAP(DCLK, PPCLK_DCLK_0),
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Completed in 537 milliseconds