| /linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.c | 1154 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000;
|
| H A D | display_mode_vba_20.c | 255 > mode_lib->vba.DCFCLK * mode_lib->vba.ReturnBusWidth / 4.0)
266 - mode_lib->vba.DCFCLK
271 CriticalCompression = 2.0 * mode_lib->vba.ReturnBusWidth * mode_lib->vba.DCFCLK
287 * mode_lib->vba.DCFCLK
1306 mode_lib->vba.ReturnBusWidth * mode_lib->vba.DCFCLK,
1319 mode_lib->vba.ReturnBusWidth * mode_lib->vba.DCFCLK,
1327 DTRACE(" dcfclk_mhz = %f", mode_lib->vba.DCFCLK);
1414 (mode_lib->vba.RoundTripPingLatencyCycles + 32) / mode_lib->vba.DCFCLK
1631 / (mode_lib->vba.DCFCLK * 64);
1660 // dml_ml->vba.DCFCLK Dee
[all...] |
| H A D | display_mode_vba_20v2.c | 279 > mode_lib->vba.DCFCLK * mode_lib->vba.ReturnBusWidth / 4.0)
290 - mode_lib->vba.DCFCLK
295 CriticalCompression = 2.0 * mode_lib->vba.ReturnBusWidth * mode_lib->vba.DCFCLK
311 * mode_lib->vba.DCFCLK
1366 mode_lib->vba.ReturnBusWidth * mode_lib->vba.DCFCLK,
1379 mode_lib->vba.ReturnBusWidth * mode_lib->vba.DCFCLK,
1387 DTRACE(" dcfclk_mhz = %f", mode_lib->vba.DCFCLK);
1474 (mode_lib->vba.RoundTripPingLatencyCycles + 32) / mode_lib->vba.DCFCLK
1667 / (mode_lib->vba.DCFCLK * 64);
1696 // dml_ml->vba.DCFCLK Dee
[all...] |
| /linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| H A D | display_mode_vba_21.c | 295 double DCFCLK,
1680 DTRACE(" dcfclk_mhz = %f", mode_lib->vba.DCFCLK);
1751 // DCFCLK Deep Sleep
2016 (mode_lib->vba.RoundTripPingLatencyCycles + 32) / mode_lib->vba.DCFCLK
2427 mode_lib->vba.DCFCLK,
2767 / (mode_lib->vba.DCFCLK * 64)
5223 mode_lib->vba.DCFCLK = mode_lib->vba.DCFCLKPerState[mode_lib->vba.VoltageLevel];
5252 double DCFCLK,
5242 CalculateWatermarksAndDRAMSpeedChangeSupport( struct display_mode_lib *mode_lib, unsigned int PrefetchMode, unsigned int NumberOfActivePlanes, unsigned int MaxLineBufferLines, unsigned int LineBufferSize, unsigned int DPPOutputBufferPixels, unsigned int DETBufferSizeInKByte, unsigned int WritebackInterfaceLumaBufferSize, unsigned int WritebackInterfaceChromaBufferSize, double DCFCLK, double UrgentOutOfOrderReturn, double ReturnBW, bool GPUVMEnable, int dpte_group_bytes[], unsigned int MetaChunkSize, double UrgentLatency, double ExtraLatency, double WritebackLatency, double WritebackChunkSize, double SOCCLK, double DRAMClockChangeLatency, double SRExitTime, double SREnterPlusExitTime, double DCFCLKDeepSleep, int DPPPerPlane[], bool DCCEnable[], double DPPCLK[], double SwathWidthSingleDPPY[], unsigned int SwathHeightY[], double ReadBandwidthPlaneLuma[], unsigned int SwathHeightC[], double ReadBandwidthPlaneChroma[], unsigned int LBBitPerPixel[], double SwathWidthY[], double HRatio[], unsigned int vtaps[], unsigned int VTAPsChroma[], double VRatio[], unsigned int HTotal[], double PixelClock[], unsigned int BlendingAndTiming[], double BytePerPixelDETY[], double BytePerPixelDETC[], bool WritebackEnable[], enum source_format_class WritebackPixelFormat[], double WritebackDestinationWidth[], double WritebackDestinationHeight[], double WritebackSourceHeight[], enum clock_change_support *DRAMClockChangeSupport, double *UrgentWatermark, double *WritebackUrgentWatermark, double *DRAMClockChangeWatermark, double *WritebackDRAMClockChangeWatermark, double *StutterExitWatermark, double *StutterEnterPlusExitWatermark, double *MinActiveDRAMClockChangeLatencySupported) argument
|
| /linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| H A D | display_mode_vba_30.c | 303 double DCFCLK,
513 double DCFCLK,
620 double DCFCLK,
1871 v->ReturnBusWidth * v->DCFCLK,
2028 DTRACE(" dcfclk_mhz = %f", v->DCFCLK);
2084 // DCFCLK Deep Sleep
2341 v->DCFCLK,
2750 v->DCFCLK,
3015 v->DCFCLK,
5181 v->DCFCLK
5191 CalculateWatermarksAndDRAMSpeedChangeSupport( struct display_mode_lib *mode_lib, unsigned int PrefetchMode, unsigned int NumberOfActivePlanes, unsigned int MaxLineBufferLines, unsigned int LineBufferSize, unsigned int DPPOutputBufferPixels, unsigned int DETBufferSizeInKByte, unsigned int WritebackInterfaceBufferSize, double DCFCLK, double ReturnBW, bool GPUVMEnable, unsigned int dpte_group_bytes[], unsigned int MetaChunkSize, double UrgentLatency, double ExtraLatency, double WritebackLatency, double WritebackChunkSize, double SOCCLK, double DRAMClockChangeLatency, double SRExitTime, double SREnterPlusExitTime, double DCFCLKDeepSleep, unsigned int DPPPerPlane[], bool DCCEnable[], double DPPCLK[], unsigned int DETBufferSizeY[], unsigned int DETBufferSizeC[], unsigned int SwathHeightY[], unsigned int SwathHeightC[], unsigned int LBBitPerPixel[], double SwathWidthY[], double SwathWidthC[], double HRatio[], double HRatioChroma[], unsigned int vtaps[], unsigned int VTAPsChroma[], double VRatio[], double VRatioChroma[], unsigned int HTotal[], double PixelClock[], unsigned int BlendingAndTiming[], double BytePerPixelDETY[], double BytePerPixelDETC[], double DSTXAfterScaler[], double DSTYAfterScaler[], bool WritebackEnable[], enum source_format_class WritebackPixelFormat[], double WritebackDestinationWidth[], double WritebackDestinationHeight[], double WritebackSourceHeight[], enum clock_change_support *DRAMClockChangeSupport, double *UrgentWatermark, double *WritebackUrgentWatermark, double *DRAMClockChangeWatermark, double *WritebackDRAMClockChangeWatermark, double *StutterExitWatermark, double *StutterEnterPlusExitWatermark, double *MinActiveDRAMClockChangeLatencySupported) argument
5946 CalculateStutterEfficiency( int NumberOfActivePlanes, long ROBBufferSizeInKByte, double TotalDataReadBandwidth, double DCFCLK, double ReturnBW, double SRExitTime, bool SynchronizedVBlank, int DPPPerPlane[], unsigned int DETBufferSizeY[], int BytePerPixelY[], double BytePerPixelDETY[], double SwathWidthY[], int SwathHeightY[], int SwathHeightC[], double DCCRateLuma[], double DCCRateChroma[], int HTotal[], int VTotal[], double PixelClock[], double VRatio[], enum scan_direction_class SourceScan[], int BlockHeight256BytesY[], int BlockWidth256BytesY[], int BlockHeight256BytesC[], int BlockWidth256BytesC[], int DCCYMaxUncompressedBlock[], int DCCCMaxUncompressedBlock[], int VActive[], bool DCCEnable[], bool WritebackEnable[], double ReadBandwidthPlaneLuma[], double ReadBandwidthPlaneChroma[], double meta_row_bw[], double dpte_row_bw[], double *StutterEfficiencyNotIncludingVBlank, double *StutterEfficiency, double *StutterPeriodOut) argument
6397 CalculateExtraLatency( long RoundTripPingLatencyCycles, long ReorderingBytes, double DCFCLK, int TotalNumberOfActiveDPP, int PixelChunkSizeInKByte, int TotalNumberOfDCCActiveDPP, int MetaChunkSize, double ReturnBW, bool GPUVMEnable, bool HostVMEnable, int NumberOfActivePlanes, int NumberOfDPP[], int dpte_group_bytes[], double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData, double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly, double HostVMMinPageSize, int HostVMMaxNonCachedPageTableLevels) argument
[all...] |
| /linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | display_mode_vba_31.c | 56 // Delay in DCFCLK from ARB to DET (1st num is ARB to SDPIF, 2nd number is SDPIF to DET)
295 double DCFCLK,
483 double DCFCLK,
606 double DCFCLK,
2158 DTRACE(" dcfclk_mhz = %f", v->DCFCLK);
2214 // DCFCLK Deep Sleep
2470 dml_min(v->ReturnBusWidth * v->DCFCLK, v->FabricClock * v->FabricDatapathToDCNDataReturn)
2477 dml_print("DML::%s: v->DCFCLK = %f\n", __func__, v->DCFCLK);
2495 v->DCFCLK,
5555 CalculateWatermarksAndDRAMSpeedChangeSupport( struct display_mode_lib *mode_lib, unsigned int PrefetchMode, double DCFCLK, double ReturnBW, double UrgentLatency, double ExtraLatency, double SOCCLK, double DCFCLKDeepSleep, unsigned int DETBufferSizeY[], unsigned int DETBufferSizeC[], unsigned int SwathHeightY[], unsigned int SwathHeightC[], double SwathWidthY[], double SwathWidthC[], unsigned int DPPPerPlane[], double BytePerPixelDETY[], double BytePerPixelDETC[], bool UnboundedRequestEnabled, int unsigned CompressedBufferSizeInkByte, enum clock_change_support *DRAMClockChangeSupport, double *StutterExitWatermark, double *StutterEnterPlusExitWatermark, double *Z8StutterExitWatermark, double *Z8StutterEnterPlusExitWatermark) argument
6306 CalculateStutterEfficiency( struct display_mode_lib *mode_lib, int CompressedBufferSizeInkByte, bool UnboundedRequestEnabled, int ConfigReturnBufferSizeInKByte, int MetaFIFOSizeInKEntries, int ZeroSizeBufferEntries, int NumberOfActivePlanes, int ROBBufferSizeInKByte, double TotalDataReadBandwidth, double DCFCLK, double ReturnBW, double COMPBUF_RESERVED_SPACE_64B, double COMPBUF_RESERVED_SPACE_ZS, double SRExitTime, double SRExitZ8Time, bool SynchronizedVBlank, double Z8StutterEnterPlusExitWatermark, double StutterEnterPlusExitWatermark, bool ProgressiveToInterlaceUnitInOPP, bool Interlace[], double MinTTUVBlank[], int DPPPerPlane[], unsigned int DETBufferSizeY[], int BytePerPixelY[], double BytePerPixelDETY[], double SwathWidthY[], int SwathHeightY[], int SwathHeightC[], double NetDCCRateLuma[], double NetDCCRateChroma[], double DCCFractionOfZeroSizeRequestsLuma[], double DCCFractionOfZeroSizeRequestsChroma[], int HTotal[], int VTotal[], double PixelClock[], double VRatio[], enum scan_direction_class SourceScan[], int BlockHeight256BytesY[], int BlockWidth256BytesY[], int BlockHeight256BytesC[], int BlockWidth256BytesC[], int DCCYMaxUncompressedBlock[], int DCCCMaxUncompressedBlock[], int VActive[], bool DCCEnable[], bool WritebackEnable[], double ReadBandwidthPlaneLuma[], double ReadBandwidthPlaneChroma[], double meta_row_bw[], double dpte_row_bw[], double *StutterEfficiencyNotIncludingVBlank, double *StutterEfficiency, int *NumberOfStutterBurstsPerFrame, double *Z8StutterEfficiencyNotIncludingVBlank, double *Z8StutterEfficiency, int *Z8NumberOfStutterBurstsPerFrame, double *StutterPeriod) argument
6930 CalculateExtraLatency( int RoundTripPingLatencyCycles, int ReorderingBytes, double DCFCLK, int TotalNumberOfActiveDPP, int PixelChunkSizeInKByte, int TotalNumberOfDCCActiveDPP, int MetaChunkSize, double ReturnBW, bool GPUVMEnable, bool HostVMEnable, int NumberOfActivePlanes, int NumberOfDPP[], int dpte_group_bytes[], double HostVMInefficiencyFactor, double HostVMMinPageSize, int HostVMMaxNonCachedPageTableLevels) argument
[all...] |
| /linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| H A D | display_mode_vba_314.c | 57 // Delay in DCFCLK from ARB to DET (1st num is ARB to SDPIF, 2nd number is SDPIF to DET)
307 double DCFCLK,
495 double DCFCLK,
617 double DCFCLK,
2179 DTRACE(" dcfclk_mhz = %f", v->DCFCLK);
2235 // DCFCLK Deep Sleep
2492 dml_min(v->ReturnBusWidth * v->DCFCLK, v->FabricClock * v->FabricDatapathToDCNDataReturn)
2499 dml_print("DML::%s: v->DCFCLK = %f\n", __func__, v->DCFCLK);
2517 v->DCFCLK,
5652 CalculateWatermarksAndDRAMSpeedChangeSupport( struct display_mode_lib *mode_lib, unsigned int PrefetchMode, double DCFCLK, double ReturnBW, double UrgentLatency, double ExtraLatency, double SOCCLK, double DCFCLKDeepSleep, unsigned int DETBufferSizeY[], unsigned int DETBufferSizeC[], unsigned int SwathHeightY[], unsigned int SwathHeightC[], double SwathWidthY[], double SwathWidthC[], unsigned int DPPPerPlane[], double BytePerPixelDETY[], double BytePerPixelDETC[], bool UnboundedRequestEnabled, unsigned int CompressedBufferSizeInkByte, enum clock_change_support *DRAMClockChangeSupport, double *StutterExitWatermark, double *StutterEnterPlusExitWatermark, double *Z8StutterExitWatermark, double *Z8StutterEnterPlusExitWatermark) argument
6404 CalculateStutterEfficiency( struct display_mode_lib *mode_lib, int CompressedBufferSizeInkByte, bool UnboundedRequestEnabled, int ConfigReturnBufferSizeInKByte, int MetaFIFOSizeInKEntries, int ZeroSizeBufferEntries, int NumberOfActivePlanes, int ROBBufferSizeInKByte, double TotalDataReadBandwidth, double DCFCLK, double ReturnBW, double COMPBUF_RESERVED_SPACE_64B, double COMPBUF_RESERVED_SPACE_ZS, double SRExitTime, double SRExitZ8Time, bool SynchronizedVBlank, double Z8StutterEnterPlusExitWatermark, double StutterEnterPlusExitWatermark, bool ProgressiveToInterlaceUnitInOPP, bool Interlace[], double MinTTUVBlank[], int DPPPerPlane[], unsigned int DETBufferSizeY[], int BytePerPixelY[], double BytePerPixelDETY[], double SwathWidthY[], int SwathHeightY[], int SwathHeightC[], double NetDCCRateLuma[], double NetDCCRateChroma[], double DCCFractionOfZeroSizeRequestsLuma[], double DCCFractionOfZeroSizeRequestsChroma[], int HTotal[], int VTotal[], double PixelClock[], double VRatio[], enum scan_direction_class SourceScan[], int BlockHeight256BytesY[], int BlockWidth256BytesY[], int BlockHeight256BytesC[], int BlockWidth256BytesC[], int DCCYMaxUncompressedBlock[], int DCCCMaxUncompressedBlock[], int VActive[], bool DCCEnable[], bool WritebackEnable[], double ReadBandwidthPlaneLuma[], double ReadBandwidthPlaneChroma[], double meta_row_bw[], double dpte_row_bw[], double *StutterEfficiencyNotIncludingVBlank, double *StutterEfficiency, int *NumberOfStutterBurstsPerFrame, double *Z8StutterEfficiencyNotIncludingVBlank, double *Z8StutterEfficiency, int *Z8NumberOfStutterBurstsPerFrame, double *StutterPeriod) argument
7023 CalculateExtraLatency( int RoundTripPingLatencyCycles, int ReorderingBytes, double DCFCLK, int TotalNumberOfActiveDPP, int PixelChunkSizeInKByte, int TotalNumberOfDCCActiveDPP, int MetaChunkSize, double ReturnBW, bool GPUVMEnable, bool HostVMEnable, int NumberOfActivePlanes, int NumberOfDPP[], int dpte_group_bytes[], double HostVMInefficiencyFactor, double HostVMMinPageSize, int HostVMMaxNonCachedPageTableLevels) argument
[all...] |
| /linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | dcn32_fpu.c | 222 /* Set B - Performance - higher clocks, using DPM[2] DCFCLK and UCLK */
1652 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000;
2403 * otherwise use arbitrary low value from spreadsheet for DCFCLK as lower is safer for watermark
2405 * DCFCLK: soc.clock_limits[2] when available
2412 dcfclk = 615; //DCFCLK Vmin_lv
2437 * DCFCLK: Min, as reported by PM FW when available
2447 dcfclk = 615; //DCFCLK Vmin_lv
2473 * DCFCLK: Min, as reported by PM FW, when available
2549 * DCFCLK: Min, as reported by PM FW, when available
2675 * Do it for DCFCLK, DISPCL
[all...] |
| H A D | display_mode_vba_32.c | 311 // DCFCLK Deep Sleep
539 mode_lib->vba.DCFCLK,
545 dml_print("DML::%s: mode_lib->vba.DCFCLK = %f\n", __func__, mode_lib->vba.DCFCLK);
582 mode_lib->vba.DCFCLK,
1194 v->DCFCLK,
1522 mode_lib->vba.DCFCLK,
1586 mode_lib->vba.DCFCLK,
3729 mode_lib->vba.DCFCLK = mode_lib->vba.DCFCLKState[mode_lib->vba.VoltageLevel][MaximumMPCCombine];
|
| H A D | display_mode_vba_util_32.c | 3282 const double DCFCLK,
3287 double IdealSDPPortBandwidth = soc->return_bus_width_bytes /*mode_lib->vba.ReturnBusWidth*/ * DCFCLK;
3307 dml_print("DML::%s: DCFCLK = %f\n", __func__, DCFCLK);
3324 const double DCFCLK, argument
3329 soc->return_bus_width_bytes * DCFCLK * soc->pct_ideal_sdp_bw_after_urgent / 100.0,
3338 dml_print("DML::%s: DCFCLK = %f\n", __func__, DCFCLK);
3349 double DCFCLK,
3382 ExtraLatency = (RoundTripPingLatencyCycles + __DML_ARB_TO_RET_DELAY__) / DCFCLK
3281 dml32_get_return_bw_mbps(const soc_bounding_box_st *soc, const int VoltageLevel, const bool HostVMEnable, const double DCFCLK, const double FabricClock, const double DRAMSpeed) argument
3348 dml32_CalculateExtraLatency( unsigned int RoundTripPingLatencyCycles, unsigned int ReorderingBytes, double DCFCLK, unsigned int TotalNumberOfActiveDPP, unsigned int PixelChunkSizeInKByte, unsigned int TotalNumberOfDCCActiveDPP, unsigned int MetaChunkSize, double ReturnBW, bool GPUVMEnable, bool HostVMEnable, unsigned int NumberOfActiveSurfaces, unsigned int NumberOfDPP[], unsigned int dpte_group_bytes[], double HostVMInefficiencyFactor, double HostVMMinPageSize, unsigned int HostVMMaxNonCachedPageTableLevels) argument
4260 dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport( struct vba_vars_st *v, unsigned int PrefetchMode, double DCFCLK, double ReturnBW, SOCParametersList mmSOCParameters, double SOCCLK, double DCFClkDeepSleep, unsigned int DETBufferSizeY[], unsigned int DETBufferSizeC[], unsigned int SwathHeightY[], unsigned int SwathHeightC[], double SwathWidthY[], double SwathWidthC[], unsigned int DPPPerSurface[], double BytePerPixelDETY[], double BytePerPixelDETC[], double DSTXAfterScaler[], double DSTYAfterScaler[], bool UnboundedRequestEnabled, unsigned int CompressedBufferSizeInkByte, enum clock_change_support *DRAMClockChangeSupport, double MaxActiveDRAMClockChangeLatencySupported[], unsigned int SubViewportLinesNeededInMALL[], enum dm_fclock_change_support *FCLKChangeSupport, double *MinActiveFCLKChangeLatencySupported, bool *USRRetrainingSupport, double ActiveDRAMClockChangeLatencyMargin[]) argument
5588 dml32_CalculateStutterEfficiency( unsigned int CompressedBufferSizeInkByte, enum dm_use_mall_for_pstate_change_mode UseMALLForPStateChange[], bool UnboundedRequestEnabled, unsigned int MetaFIFOSizeInKEntries, unsigned int ZeroSizeBufferEntries, unsigned int PixelChunkSizeInKByte, unsigned int NumberOfActiveSurfaces, unsigned int ROBBufferSizeInKByte, double TotalDataReadBandwidth, double DCFCLK, double ReturnBW, unsigned int CompbufReservedSpace64B, unsigned int CompbufReservedSpaceZs, double SRExitTime, double SRExitZ8Time, bool SynchronizeTimingsFinal, unsigned int BlendingAndTiming[], double StutterEnterPlusExitWatermark, double Z8StutterEnterPlusExitWatermark, bool ProgressiveToInterlaceUnitInOPP, bool Interlace[], double MinTTUVBlank[], unsigned int DPPPerSurface[], unsigned int DETBufferSizeY[], unsigned int BytePerPixelY[], double BytePerPixelDETY[], double SwathWidthY[], unsigned int SwathHeightY[], unsigned int SwathHeightC[], double NetDCCRateLuma[], double NetDCCRateChroma[], double DCCFractionOfZeroSizeRequestsLuma[], double DCCFractionOfZeroSizeRequestsChroma[], unsigned int HTotal[], unsigned int VTotal[], double PixelClock[], double VRatio[], enum dm_rotation_angle SourceRotation[], unsigned int BlockHeight256BytesY[], unsigned int BlockWidth256BytesY[], unsigned int BlockHeight256BytesC[], unsigned int BlockWidth256BytesC[], unsigned int DCCYMaxUncompressedBlock[], unsigned int DCCCMaxUncompressedBlock[], unsigned int VActive[], bool DCCEnable[], bool WritebackEnable[], double ReadBandwidthSurfaceLuma[], double ReadBandwidthSurfaceChroma[], double meta_row_bw[], double dpte_row_bw[], double *StutterEfficiencyNotIncludingVBlank, double *StutterEfficiency, unsigned int *NumberOfStutterBurstsPerFrame, double *Z8StutterEfficiencyNotIncludingVBlank, double *Z8StutterEfficiency, unsigned int *Z8NumberOfStutterBurstsPerFrame, double *StutterPeriod, bool *DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE) argument
[all...] |
| H A D | display_mode_vba_util_32.h | 693 const double DCFCLK,
699 const double DCFCLK,
706 double DCFCLK,
807 double DCFCLK,
1003 double DCFCLK,
|
| /linux-master/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_vba.c | 380 mode_lib->vba.DCFCLK = soc->clock_limits[i].dcfclk_mhz;
1093 mode_lib->vba.DCFCLK = mode_lib->vba.cache_pipes[0].clks_cfg.dcfclk_mhz;
|
| H A D | display_mode_vba.h | 438 double DCFCLK; member in struct:vba_vars_st
|
| /linux-master/drivers/gpu/drm/amd/display/dc/dml2/ |
| H A D | display_mode_core.c | 619 dml_float_t DCFCLK,
3966 dml_print("DML::%s: DCFCLK = %f\n", __func__, p->DCFCLK);
3969 StutterBurstTime = PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer / AverageDCCCompressionRate / p->ReturnBW + (*p->StutterPeriod * p->TotalDataReadBandwidth - PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer) / (p->DCFCLK * 64) + *p->StutterPeriod * TotalRowReadBandwidth / p->ReturnBW;
3973 dml_print("DML::%s: Part 2 = %f\n", __func__, (*p->StutterPeriod * p->TotalDataReadBandwidth - PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer) / (p->DCFCLK * 64));
4462 dml_float_t DCFCLK,
4495 ExtraLatency = (RoundTripPingLatencyCycles + __DML_ARB_TO_RET_DELAY__) / DCFCLK + ExtraLatencyBytes / ReturnBW;
4499 dml_print("DML::%s: DCFCLK=%f\n", __func__, DCFCLK);
5767 dml_float_t DCFCLK,
4459 CalculateExtraLatency( dml_uint_t RoundTripPingLatencyCycles, dml_uint_t ReorderingBytes, dml_float_t DCFCLK, dml_uint_t TotalNumberOfActiveDPP, dml_uint_t PixelChunkSizeInKByte, dml_uint_t TotalNumberOfDCCActiveDPP, dml_uint_t MetaChunkSize, dml_float_t ReturnBW, dml_bool_t GPUVMEnable, dml_bool_t HostVMEnable, dml_uint_t NumberOfActiveSurfaces, dml_uint_t NumberOfDPP[], dml_uint_t dpte_group_bytes[], dml_float_t HostVMInefficiencyFactor, dml_uint_t HostVMMinPageSize, dml_uint_t HostVMMaxNonCachedPageTableLevels) argument
5763 dml_get_return_bw_mbps_vm_only( const struct soc_bounding_box_st *soc, dml_bool_t use_ideal_dram_bw_strobe, dml_bool_t HostVMEnable, dml_float_t DCFCLK, dml_float_t FabricClock, dml_float_t DRAMSpeed) argument
5789 dml_get_return_bw_mbps( const struct soc_bounding_box_st *soc, dml_bool_t use_ideal_dram_bw_strobe, dml_bool_t HostVMEnable, dml_float_t DCFCLK, dml_float_t FabricClock, dml_float_t DRAMSpeed) argument
[all...] |
| H A D | display_mode_core.h | 52 dml_float_t DCFCLK,
60 dml_float_t DCFCLK,
|
| H A D | display_mode_core_structs.h | 644 dml_bool_t UseMinimumRequiredDCFCLK; //<brief When set the mode_check stage will figure the min DCFCLK freq to support the given display configuration. User can tell use the output DCFCLK for mode programming.
768 dml_float_t DCFCLKState[2]; /// <brief recommended DCFCLK freq; calculated by DML. If UseMinimumRequiredDCFCLK is not set; then it will be just the state DCFCLK; else it will min DCFCLK for support
775 dml_float_t DCFCLK; /// <brief Basically just the clock freq at the min (or given) state and max combine setting member in struct:mode_support_st
1277 dml_float_t DCFCLK; member in struct:CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params_st
1473 dml_float_t DCFCLK; member in struct:CalculateStutterEfficiency_params_st
|