Searched refs:CWL (Results 1 - 4 of 4) sorted by relevance

/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dsddr3.c72 int CWL, CL, WR, DLL = 0, ODT = 0; local
79 /* XXX: NV50: Get CWL from the timing register */
82 CWL = ram->next->bios.timing_10_CWL;
88 CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7;
100 CWL = ramxlat(ramddr3_cwl, CWL);
103 if (CL < 0 || CWL < 0 || WR < 0)
118 ram->mr[2] |= (CWL & 0x07) << 3;
H A Dgddr3.c73 int CL, WR, CWL, DLL = 0, ODT = 0, RON, hi; local
77 CWL = ram->next->bios.timing_10_CWL;
85 CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7;
104 if (CL < 0 || CWL < 1 || CWL > 7 || WR < 0)
108 ram->mr[0] |= (CWL & 0x07) << 9;
H A Dramnv50.c86 switch ((!T(CWL)) * ram->base.type) {
88 T(CWL) = T(CL) - 1;
91 T(CWL) = ((cur2 & 0xff000000) >> 24) + 1;
98 timing[6] = (0x2d + T(CL) - T(CWL) +
100 T(CWL) << 8 |
101 (0x2f + T(CL) - T(CWL));
104 timing[6] = (0x2b + T(CL) - T(CWL)) << 16 |
105 max_t(s8, T(CWL) - 2, 1) << 8 |
106 (0x2e + T(CL) - T(CWL));
110 timing[1] = (T(WR) + 1 + T(CWL)) << 2
[all...]
H A Dramgt215.c362 switch ((!T(CWL)) * ram->base.type) {
364 T(CWL) = T(CL) - 1;
367 T(CWL) = ((cur2 & 0xff000000) >> 24) + 1;
375 timing[1] = (T(WR) + 1 + T(CWL)) << 24 |
377 (T(WTR) + 1 + T(CWL)) << 8 |
378 (5 + T(CL) - T(CWL));
379 timing[2] = (T(CWL) - 1) << 24 |
393 max_t(u8, (T(CWL) + 6), (T(CL) + 2)) << 8 |
396 max_t(u8, 1, (6 - T(CL) + T(CWL))) << 8 |
397 (0x50 + T(CL) - T(CWL));
[all...]

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