Searched refs:CTR (Results 1 - 8 of 8) sorted by relevance

/linux-master/tools/perf/arch/powerpc/tests/
H A Dregs_load.S38 #define CTR 35 * 8 define
88 /* Store CTR */
90 std 4, CTR(3)
/linux-master/arch/x86/crypto/
H A Daesni-intel_avx-x86_64.S969 .macro INITIAL_BLOCKS_AVX REP num_initial_blocks T1 T2 T3 T4 T5 CTR XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 T6 T_key ENC_DEC
975 vmovdqu CurCount(arg2), \CTR
980 vpaddd ONE(%rip), \CTR, \CTR # INCR Y0
981 vmovdqa \CTR, reg_i
1058 vpaddd ONE(%rip), \CTR, \CTR # INCR Y0
1059 vmovdqa \CTR, \XMM1
1062 vpaddd ONE(%rip), \CTR, \CTR # INC
[all...]
H A Daesni-intel_asm.S142 #define CTR %xmm11 define
2714 * CTR: == IV, in little endian
2715 * TCTR_LOW: == lower qword of CTR
2721 movaps IV, CTR
2722 pshufb BSWAP_MASK, CTR
2725 movq CTR, TCTR_LOW
2734 * CTR: == IV, in little endian
2735 * TCTR_LOW: == lower qword of CTR
2741 * CTR: == output IV, in little endian
2742 * TCTR_LOW: == lower qword of CTR
[all...]
/linux-master/arch/arm64/crypto/
H A Daes-modes.S315 * This macro generates the code for CTR and XCTR mode.
328 CTR .req x11 // XCTR only
339 * Keep 64 bits of the IV in a register. For CTR mode this lets us
368 add CTR, CTR, BLOCKS
378 sub x6, CTR, #MAX_STRIDE - 1
379 sub x7, CTR, #MAX_STRIDE - 2
380 sub x8, CTR, #MAX_STRIDE - 3
381 sub x9, CTR, #MAX_STRIDE - 4
382 ST5( sub x10, CTR, #MAX_STRID
[all...]
/linux-master/arch/s390/crypto/
H A Dchacha-s390.S50 #define CTR %v26 define
95 VL CTR,0x50,,%r7
108 VAF XD0,XD0,CTR
245 VAF XD0,XD0,CTR
/linux-master/drivers/platform/x86/intel/telemetry/
H A Ddebugfs.c76 #define TELEM_CHECK_AND_PARSE_CTRS(EVTID, CTR) { \
78 (CTR) = evtlog[index].telem_evtlog; \
/linux-master/arch/arm/crypto/
H A Daes-ce-core.S3 * aes-ce-core.S - AES in CBC/CTR/XTS mode using ARMv8 Crypto Extensions
449 vst1.8 {q7}, [r5] @ return next CTR value
/linux-master/drivers/platform/x86/
H A Dsony-laptop.c711 SNC_HANDLE(CTR, snc_CTR_get, snc_CTR_set, NULL, 1),

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