Searched refs:CP_MEC_CNTL (Results 1 - 4 of 4) sorted by path

/linux-master/drivers/gpu/drm/radeon/
H A Dcikd.h1094 #define CP_MEC_CNTL 0x8234 macro
1098 #define CP_MEC_CNTL 0x8234 macro
H A Dcik.c4220 WREG32(CP_MEC_CNTL, 0);
4231 WREG32(CP_MEC_CNTL, (MEC_ME1_HALT | MEC_ME2_HALT));
4950 WREG32(CP_MEC_CNTL, MEC_ME1_HALT | MEC_ME2_HALT);
5154 WREG32(CP_MEC_CNTL, MEC_ME1_HALT | MEC_ME2_HALT);
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v11_0.c3392 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 0);
3394 data = REG_SET_FIELD(data, CP_MEC_CNTL,
3397 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 1);
3398 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME2_HALT, 1);
/linux-master/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dsmu8_smumgr.c193 tmp = PHM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1);
194 tmp = PHM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1);

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