Searched refs:CPU_TOPOLOGY_SMT (Results 1 - 7 of 7) sorted by relevance

/haiku/headers/private/kernel/
H A Dcpu.h32 CPU_TOPOLOGY_SMT, enumerator in enum:cpu_topology_level
/haiku/src/system/kernel/
H A Dcpu.cpp211 if (level != CPU_TOPOLOGY_SMT) {
243 if (node->children[count]->level != CPU_TOPOLOGY_SMT)
291 ASSERT(node->level == CPU_TOPOLOGY_SMT);
H A Dsystem_info.cpp424 while (node->level != CPU_TOPOLOGY_SMT) {
H A Dint.cpp418 while (node->level != CPU_TOPOLOGY_SMT) {
/haiku/src/system/kernel/arch/riscv64/
H A Darch_cpu.cpp58 cpu->topology_id[CPU_TOPOLOGY_SMT] = 0;
/haiku/src/system/kernel/scheduler/
H A Dscheduler.cpp592 case CPU_TOPOLOGY_SMT:
631 if (gCPU[i].topology_id[CPU_TOPOLOGY_SMT] == 0)
637 if (gCPU[i].topology_id[CPU_TOPOLOGY_SMT] == 0
/haiku/src/system/kernel/arch/x86/
H A Darch_cpu.cpp658 sHierarchyMask[CPU_TOPOLOGY_SMT] = kMaxSMTID - 1;
659 sHierarchyShift[CPU_TOPOLOGY_SMT] = 0;
663 = count_set_bits(sHierarchyMask[CPU_TOPOLOGY_SMT]);
665 const uint32 kSinglePackageMask = sHierarchyMask[CPU_TOPOLOGY_SMT]
738 = coresCount * (sHierarchyMask[CPU_TOPOLOGY_SMT] + 1);
793 hierarchyLevels[CPU_TOPOLOGY_SMT] = levelValue;
935 cpu->topology_id[CPU_TOPOLOGY_SMT]
936 = get_topology_level_id(topologyID, CPU_TOPOLOGY_SMT);
952 cpu->topology_id[CPU_TOPOLOGY_SMT]);

Completed in 132 milliseconds