Searched refs:CLK_MUX_READ_ONLY (Results 1 - 15 of 15) sorted by relevance

/linux-master/drivers/clk/zynqmp/
H A Dclk-mux-zynqmp.c111 ccf_flag |= CLK_MUX_READ_ONLY;
146 if (nodes->type_flag & CLK_MUX_READ_ONLY)
/linux-master/drivers/clk/rockchip/
H A Dclk-half-divider.c186 mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops
H A Dclk.c67 mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops
H A Dclk-rk3568.c533 RK3568_CLKSEL_CON(6), 6, 2, MFLAGS | CLK_MUX_READ_ONLY, 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
536 RK3568_CLKSEL_CON(6), 11, 1, MFLAGS | CLK_MUX_READ_ONLY),
H A Dclk-rk3588.c1335 RK3588_CLKSEL_CON(165), 6, 2, MFLAGS | CLK_MUX_READ_ONLY,
/linux-master/drivers/clk/
H A Dclk-mux.c177 if (clk_mux_flags & CLK_MUX_READ_ONLY)
/linux-master/drivers/clk/nxp/
H A Dclk-lpc32xx.c1114 .ops = (_flags & CLK_MUX_READ_ONLY ? \
1236 CLK_MUX_READ_ONLY),
1238 CLK_MUX_READ_ONLY),
1240 CLK_MUX_READ_ONLY),
1243 CLK_MUX_READ_ONLY),
1245 CLK_MUX_READ_ONLY),
1327 LPC32XX_DEFINE_MUX(SYS, SYSCLK_CTRL, 0, 0x1, NULL, CLK_MUX_READ_ONLY),
H A Dclk-lpc18xx-cgu.c220 LPC1XX_CGU_BASE_CLK(SAFE, base_irc_src_ids, CLK_MUX_READ_ONLY),
/linux-master/drivers/clk/renesas/
H A Drzg2l-cpg.h165 .mux_flags = CLK_MUX_READ_ONLY)
/linux-master/drivers/clk/samsung/
H A Dclk-s5pv210.c370 CLK_MUX_READ_ONLY, 0),
H A Dclk-s3c64xx.c125 MUX_F(0, "mout_syncmux", hclkx2_p, OTHERS, 6, 1, 0, CLK_MUX_READ_ONLY),
/linux-master/drivers/clk/imx/
H A Dclk.h209 __imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, CLK_SET_RATE_PARENT, CLK_MUX_READ_ONLY)
/linux-master/drivers/pinctrl/tegra/
H A Dpinctrl-tegra20.c2238 pmx->regs[1] + 0x8, 2, 2, CLK_MUX_READ_ONLY, NULL);
2241 pmx->regs[1] + 0x8, 4, 2, CLK_MUX_READ_ONLY, NULL);
/linux-master/include/linux/
H A Dclk-provider.h959 * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
982 #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */ macro
/linux-master/drivers/clk/stm32/
H A Dclk-stm32mp1.c924 element->mux.flags = CLK_MUX_READ_ONLY;

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