Searched refs:AddrReg (Results 1 - 23 of 23) sorted by path

/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp2913 Register AddrReg = MI.getOperand(1).getReg(); local
2933 const LLT OffsetTy = LLT::scalar(MRI.getType(AddrReg).getScalarSizeInBits());
2951 MIRBuilder.materializePtrAdd(NewAddrReg, AddrReg, OffsetTy, ByteOffset);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CallLowering.cpp65 Register AddrReg = MRI.createGenericVirtualRegister(LLT::pointer(0, 64)); variable
66 MIRBuilder.buildFrameIndex(AddrReg, FI);
68 return AddrReg;
162 Register AddrReg = MRI.createGenericVirtualRegister(p0); variable
163 MIRBuilder.buildPtrAdd(AddrReg, SPReg, OffsetReg);
166 return AddrReg;
H A DAArch64ExpandPseudoInsts.cpp186 Register AddrReg = MI.getOperand(2).getReg(); local
208 .addReg(AddrReg);
225 .addReg(AddrReg);
266 Register AddrReg = MI.getOperand(3).getReg(); local
289 .addReg(AddrReg);
318 .addReg(AddrReg);
H A DAArch64FastISel.cpp231 bool emitStoreRelease(MVT VT, unsigned SrcReg, unsigned AddrReg,
2090 unsigned AddrReg,
2103 AddrReg = constrainOperandRegClass(II, AddrReg, 1);
2106 .addReg(AddrReg)
2230 unsigned AddrReg = getRegForValue(PtrV); local
2231 return emitStoreRelease(VT, SrcReg, AddrReg,
2552 unsigned AddrReg = getRegForValue(BI->getOperand(0)); local
2553 if (AddrReg == 0)
2558 AddrReg
2089 emitStoreRelease(MVT VT, unsigned SrcReg, unsigned AddrReg, MachineMemOperand *MMO) argument
5123 const unsigned AddrReg = constrainOperandRegClass( local
[all...]
H A DAArch64SIMDInstrOpt.cpp504 unsigned SeqReg, AddrReg; local
518 AddrReg = MI.getOperand(1).getReg();
572 .addReg(AddrReg)
612 .addReg(AddrReg)
617 .addReg(AddrReg)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.cpp740 unsigned AddrReg = MI->getOperand(OpNum++).getReg(); local
741 O << ", [" << getRegisterName(AddrReg) << ']';
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp87 Register AddrReg = MRI.createGenericVirtualRegister( variable
89 MIRBuilder.buildFrameIndex(AddrReg, FI);
91 return AddrReg;
H A DR600InstrInfo.cpp1125 unsigned AddrReg;
1128 case 0: AddrReg = R600::R600_AddrRegClass.getRegister(Address); break;
1129 case 1: AddrReg = R600::R600_Addr_YRegClass.getRegister(Address); break;
1130 case 2: AddrReg = R600::R600_Addr_ZRegClass.getRegister(Address); break;
1131 case 3: AddrReg = R600::R600_Addr_WRegClass.getRegister(Address); break;
1138 AddrReg, ValueReg)
1157 unsigned AddrReg;
1160 case 0: AddrReg = R600::R600_AddrRegClass.getRegister(Address); break;
1161 case 1: AddrReg = R600::R600_Addr_YRegClass.getRegister(Address); break;
1162 case 2: AddrReg
[all...]
H A DSIInstrInfo.cpp330 const MachineOperand *AddrReg = getNamedOperand(LdSt, AMDGPU::OpName::vaddr); local
331 if (AddrReg && !AddrReg->isFI())
347 const MachineOperand *AddrReg = getNamedOperand(LdSt, AMDGPU::OpName::vaddr); local
348 if (!AddrReg)
353 BaseOp = AddrReg;
H A DSILoadStoreOptimizer.cpp131 const MachineOperand *AddrReg[5]; member in struct:__anon2119::SILoadStoreOptimizer::CombineInfo
138 if (AddrReg[i]->isImm() || AddrRegNext.isImm()) {
139 if (AddrReg[i]->isImm() != AddrRegNext.isImm() ||
140 AddrReg[i]->getImm() != AddrRegNext.getImm()) {
148 if (AddrReg[i]->getReg() != AddrRegNext.getReg() ||
149 AddrReg[i]->getSubReg() != AddrRegNext.getSubReg()) {
158 const MachineOperand *AddrOp = AddrReg[i];
548 AddrReg[i] = &I->getOperand(AddrIdx[i]);
958 const auto *AddrReg = TII->getNamedOperand(*CI.I, AMDGPU::OpName::addr); local
988 Register BaseReg = AddrReg
1057 const MachineOperand *AddrReg = local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCExpandPseudos.cpp62 unsigned AddrReg = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); local
65 BuildMI(*SI.getParent(), SI, SI.getDebugLoc(), TII->get(AddOpc), AddrReg)
71 .addReg(AddrReg)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallLowering.cpp108 Register AddrReg = MRI.createGenericVirtualRegister(p0); variable
109 MIRBuilder.buildPtrAdd(AddrReg, SPReg, OffsetReg);
112 return AddrReg;
302 Register AddrReg = variable
304 MIRBuilder.buildFrameIndex(AddrReg, FI);
306 return AddrReg;
H A DARMExpandPseudoInsts.cpp940 Register AddrReg = MI.getOperand(2).getReg(); local
969 MIB.addReg(AddrReg);
993 .addReg(AddrReg);
1059 Register AddrReg = MI.getOperand(2).getReg(); local
1087 MIB.addReg(AddrReg).add(predOps(ARMCC::AL));
1116 MIB.addReg(AddrReg).add(predOps(ARMCC::AL));
H A DARMFastISel.cpp1334 unsigned AddrReg = getRegForValue(I->getOperand(0)); local
1335 if (AddrReg == 0) return false;
1341 TII.get(Opc)).addReg(AddrReg));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsNaClELFStreamer.cpp101 void emitMask(unsigned AddrReg, unsigned MaskReg, argument
105 MaskInst.addOperand(MCOperand::createReg(AddrReg));
106 MaskInst.addOperand(MCOperand::createReg(AddrReg));
114 unsigned AddrReg = MI.getOperand(0).getReg(); local
117 emitMask(AddrReg, IndirectBranchMaskReg, STI);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsCallLowering.cpp195 Register AddrReg = MRI.createGenericVirtualRegister(LLT::pointer(0, 32)); local
196 MIRBuilder.buildFrameIndex(AddrReg, FI);
198 return AddrReg;
301 Register AddrReg = MRI.createGenericVirtualRegister(p0); local
302 MIRBuilder.buildPtrAdd(AddrReg, SPReg, OffsetReg);
310 return AddrReg;
H A DMipsISelLowering.cpp2550 unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0; local
2552 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1));
2555 DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())),
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp1857 unsigned AddrReg = getRegForValue(I->getOperand(0)); local
1858 if (AddrReg == 0)
1862 .addReg(AddrReg);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVExpandPseudoInsts.cpp240 Register AddrReg = MI.getOperand(2).getReg(); local
251 .addReg(AddrReg);
265 .addReg(AddrReg)
302 Register AddrReg = MI.getOperand(2).getReg(); local
317 .addReg(AddrReg);
350 .addReg(AddrReg)
442 Register AddrReg = MI.getOperand(3).getReg(); local
457 .addReg(AddrReg);
509 .addReg(AddrReg)
554 Register AddrReg local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CallLowering.cpp117 Register AddrReg = MRI.createGenericVirtualRegister(p0); variable
118 MIRBuilder.buildPtrAdd(AddrReg, SPReg, OffsetReg);
121 return AddrReg;
243 Register AddrReg = MRI.createGenericVirtualRegister( variable
245 MIRBuilder.buildFrameIndex(AddrReg, FI);
246 return AddrReg;
H A DX86FastISel.cpp3793 unsigned AddrReg = createResultReg(&X86::GR64RegClass); local
3795 AddrReg)
3799 addDirectMem(MIB, AddrReg);
H A DX86InstructionSelector.cpp1453 Register AddrReg = MRI.createVirtualRegister(&X86::GR64RegClass); local
1454 BuildMI(*I.getParent(), I, DbgLoc, TII.get(X86::MOV64ri), AddrReg)
1463 AddrReg)
H A DX86SpeculativeLoadHardening.cpp1156 Register AddrReg = MRI->createVirtualRegister(&X86::GR64RegClass); local
1158 BuildMI(MBB, InsertPt, DebugLoc(), TII->get(X86::LEA64r), AddrReg)
1169 .addReg(AddrReg, RegState::Kill);

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