Searched refs:newval (Results 1 - 25 of 101) sorted by relevance

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/netbsd-6-1-5-RELEASE/external/gpl3/gdb/dist/sim/cris/
H A Dcpuv32.c42 crisv32f_h_v32_v32_set (SIM_CPU *current_cpu, BI newval) argument
44 SET_H_V32_V32 (newval);
58 crisv32f_h_pc_set (SIM_CPU *current_cpu, USI newval) argument
60 SET_H_PC (newval);
74 crisv32f_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval) argument
76 SET_H_GR (regno, newval);
90 crisv32f_h_gr_acr_set (SIM_CPU *current_cpu, UINT regno, SI newval) argument
92 CPU (h_gr_acr[regno]) = newval;
106 crisv32f_h_raw_gr_acr_set (SIM_CPU *current_cpu, UINT regno, SI newval) argument
108 SET_H_RAW_GR_ACR (regno, newval);
122 crisv32f_h_sr_set(SIM_CPU *current_cpu, UINT regno, SI newval) argument
138 crisv32f_h_sr_v32_set(SIM_CPU *current_cpu, UINT regno, SI newval) argument
154 crisv32f_h_supr_set(SIM_CPU *current_cpu, UINT regno, SI newval) argument
170 crisv32f_h_cbit_set(SIM_CPU *current_cpu, BI newval) argument
186 crisv32f_h_cbit_move_set(SIM_CPU *current_cpu, BI newval) argument
202 crisv32f_h_cbit_move_v32_set(SIM_CPU *current_cpu, BI newval) argument
218 crisv32f_h_vbit_set(SIM_CPU *current_cpu, BI newval) argument
234 crisv32f_h_vbit_move_set(SIM_CPU *current_cpu, BI newval) argument
250 crisv32f_h_vbit_move_v32_set(SIM_CPU *current_cpu, BI newval) argument
266 crisv32f_h_zbit_set(SIM_CPU *current_cpu, BI newval) argument
282 crisv32f_h_zbit_move_set(SIM_CPU *current_cpu, BI newval) argument
298 crisv32f_h_zbit_move_v32_set(SIM_CPU *current_cpu, BI newval) argument
314 crisv32f_h_nbit_set(SIM_CPU *current_cpu, BI newval) argument
330 crisv32f_h_nbit_move_set(SIM_CPU *current_cpu, BI newval) argument
346 crisv32f_h_nbit_move_v32_set(SIM_CPU *current_cpu, BI newval) argument
362 crisv32f_h_xbit_set(SIM_CPU *current_cpu, BI newval) argument
378 crisv32f_h_ibit_set(SIM_CPU *current_cpu, BI newval) argument
394 crisv32f_h_pbit_set(SIM_CPU *current_cpu, BI newval) argument
410 crisv32f_h_rbit_set(SIM_CPU *current_cpu, BI newval) argument
426 crisv32f_h_ubit_set(SIM_CPU *current_cpu, BI newval) argument
442 crisv32f_h_gbit_set(SIM_CPU *current_cpu, BI newval) argument
458 crisv32f_h_kernel_sp_set(SIM_CPU *current_cpu, SI newval) argument
474 crisv32f_h_ubit_v32_set(SIM_CPU *current_cpu, BI newval) argument
490 crisv32f_h_ibit_v32_set(SIM_CPU *current_cpu, BI newval) argument
506 crisv32f_h_mbit_set(SIM_CPU *current_cpu, BI newval) argument
522 crisv32f_h_qbit_set(SIM_CPU *current_cpu, BI newval) argument
538 crisv32f_h_sbit_set(SIM_CPU *current_cpu, BI newval) argument
554 crisv32f_h_insn_prefixed_p_set(SIM_CPU *current_cpu, BI newval) argument
570 crisv32f_h_insn_prefixed_p_v32_set(SIM_CPU *current_cpu, BI newval) argument
586 crisv32f_h_prefixreg_v32_set(SIM_CPU *current_cpu, SI newval) argument
[all...]
H A Dcpuv10.c42 crisv10f_h_v32_non_v32_set (SIM_CPU *current_cpu, BI newval) argument
44 SET_H_V32_NON_V32 (newval);
58 crisv10f_h_pc_set (SIM_CPU *current_cpu, USI newval) argument
60 SET_H_PC (newval);
74 crisv10f_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval) argument
76 SET_H_GR (regno, newval);
90 crisv10f_h_gr_pc_set (SIM_CPU *current_cpu, UINT regno, SI newval) argument
92 SET_H_GR_PC (regno, newval);
106 crisv10f_h_gr_real_pc_set (SIM_CPU *current_cpu, UINT regno, SI newval) argument
108 CPU (h_gr_real_pc[regno]) = newval;
122 crisv10f_h_raw_gr_pc_set(SIM_CPU *current_cpu, UINT regno, SI newval) argument
138 crisv10f_h_sr_set(SIM_CPU *current_cpu, UINT regno, SI newval) argument
154 crisv10f_h_sr_v10_set(SIM_CPU *current_cpu, UINT regno, SI newval) argument
170 crisv10f_h_cbit_set(SIM_CPU *current_cpu, BI newval) argument
186 crisv10f_h_cbit_move_set(SIM_CPU *current_cpu, BI newval) argument
202 crisv10f_h_cbit_move_pre_v32_set(SIM_CPU *current_cpu, BI newval) argument
218 crisv10f_h_vbit_set(SIM_CPU *current_cpu, BI newval) argument
234 crisv10f_h_vbit_move_set(SIM_CPU *current_cpu, BI newval) argument
250 crisv10f_h_vbit_move_pre_v32_set(SIM_CPU *current_cpu, BI newval) argument
266 crisv10f_h_zbit_set(SIM_CPU *current_cpu, BI newval) argument
282 crisv10f_h_zbit_move_set(SIM_CPU *current_cpu, BI newval) argument
298 crisv10f_h_zbit_move_pre_v32_set(SIM_CPU *current_cpu, BI newval) argument
314 crisv10f_h_nbit_set(SIM_CPU *current_cpu, BI newval) argument
330 crisv10f_h_nbit_move_set(SIM_CPU *current_cpu, BI newval) argument
346 crisv10f_h_nbit_move_pre_v32_set(SIM_CPU *current_cpu, BI newval) argument
362 crisv10f_h_xbit_set(SIM_CPU *current_cpu, BI newval) argument
378 crisv10f_h_ibit_set(SIM_CPU *current_cpu, BI newval) argument
394 crisv10f_h_ibit_pre_v32_set(SIM_CPU *current_cpu, BI newval) argument
410 crisv10f_h_pbit_set(SIM_CPU *current_cpu, BI newval) argument
426 crisv10f_h_ubit_set(SIM_CPU *current_cpu, BI newval) argument
442 crisv10f_h_ubit_pre_v32_set(SIM_CPU *current_cpu, BI newval) argument
458 crisv10f_h_insn_prefixed_p_set(SIM_CPU *current_cpu, BI newval) argument
474 crisv10f_h_insn_prefixed_p_pre_v32_set(SIM_CPU *current_cpu, BI newval) argument
490 crisv10f_h_prefixreg_pre_v32_set(SIM_CPU *current_cpu, SI newval) argument
[all...]
/netbsd-6-1-5-RELEASE/external/gpl3/gdb/dist/sim/sh64/
H A Dcpu.c42 sh64_h_pc_set (SIM_CPU *current_cpu, UDI newval) argument
44 SET_H_PC (newval);
58 sh64_h_gr_set (SIM_CPU *current_cpu, UINT regno, DI newval) argument
60 SET_H_GR (regno, newval);
74 sh64_h_grc_set (SIM_CPU *current_cpu, UINT regno, SI newval) argument
76 SET_H_GRC (regno, newval);
90 sh64_h_cr_set (SIM_CPU *current_cpu, UINT regno, DI newval) argument
92 SET_H_CR (regno, newval);
106 sh64_h_sr_set (SIM_CPU *current_cpu, SI newval) argument
108 CPU (h_sr) = newval;
122 sh64_h_fpscr_set(SIM_CPU *current_cpu, SI newval) argument
138 sh64_h_frbit_set(SIM_CPU *current_cpu, BI newval) argument
154 sh64_h_szbit_set(SIM_CPU *current_cpu, BI newval) argument
170 sh64_h_prbit_set(SIM_CPU *current_cpu, BI newval) argument
186 sh64_h_sbit_set(SIM_CPU *current_cpu, BI newval) argument
202 sh64_h_mbit_set(SIM_CPU *current_cpu, BI newval) argument
218 sh64_h_qbit_set(SIM_CPU *current_cpu, BI newval) argument
234 sh64_h_fr_set(SIM_CPU *current_cpu, UINT regno, SF newval) argument
250 sh64_h_fp_set(SIM_CPU *current_cpu, UINT regno, SF newval) argument
266 sh64_h_fv_set(SIM_CPU *current_cpu, UINT regno, SF newval) argument
282 sh64_h_fmtx_set(SIM_CPU *current_cpu, UINT regno, SF newval) argument
298 sh64_h_dr_set(SIM_CPU *current_cpu, UINT regno, DF newval) argument
314 sh64_h_fsd_set(SIM_CPU *current_cpu, UINT regno, DF newval) argument
330 sh64_h_fmov_set(SIM_CPU *current_cpu, UINT regno, DF newval) argument
346 sh64_h_tr_set(SIM_CPU *current_cpu, UINT regno, DI newval) argument
362 sh64_h_endian_set(SIM_CPU *current_cpu, BI newval) argument
378 sh64_h_ism_set(SIM_CPU *current_cpu, BI newval) argument
394 sh64_h_frc_set(SIM_CPU *current_cpu, UINT regno, SF newval) argument
410 sh64_h_drc_set(SIM_CPU *current_cpu, UINT regno, DF newval) argument
426 sh64_h_xf_set(SIM_CPU *current_cpu, UINT regno, SF newval) argument
442 sh64_h_xd_set(SIM_CPU *current_cpu, UINT regno, DF newval) argument
458 sh64_h_fvc_set(SIM_CPU *current_cpu, UINT regno, SF newval) argument
474 sh64_h_gbr_set(SIM_CPU *current_cpu, SI newval) argument
490 sh64_h_vbr_set(SIM_CPU *current_cpu, SI newval) argument
506 sh64_h_pr_set(SIM_CPU *current_cpu, SI newval) argument
522 sh64_h_macl_set(SIM_CPU *current_cpu, SI newval) argument
538 sh64_h_mach_set(SIM_CPU *current_cpu, SI newval) argument
554 sh64_h_tbit_set(SIM_CPU *current_cpu, BI newval) argument
[all...]
/netbsd-6-1-5-RELEASE/external/gpl3/gdb/dist/sim/m32r/
H A Dcpu2.c42 m32r2f_h_pc_set (SIM_CPU *current_cpu, USI newval) argument
44 CPU (h_pc) = newval;
58 m32r2f_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval) argument
60 CPU (h_gr[regno]) = newval;
74 m32r2f_h_cr_set (SIM_CPU *current_cpu, UINT regno, USI newval) argument
76 SET_H_CR (regno, newval);
90 m32r2f_h_accum_set (SIM_CPU *current_cpu, DI newval) argument
92 SET_H_ACCUM (newval);
106 m32r2f_h_accums_set (SIM_CPU *current_cpu, UINT regno, DI newval) argument
108 SET_H_ACCUMS (regno, newval);
122 m32r2f_h_cond_set(SIM_CPU *current_cpu, BI newval) argument
138 m32r2f_h_psw_set(SIM_CPU *current_cpu, UQI newval) argument
154 m32r2f_h_bpsw_set(SIM_CPU *current_cpu, UQI newval) argument
170 m32r2f_h_bbpsw_set(SIM_CPU *current_cpu, UQI newval) argument
186 m32r2f_h_lock_set(SIM_CPU *current_cpu, BI newval) argument
[all...]
H A Dcpux.c42 m32rxf_h_pc_set (SIM_CPU *current_cpu, USI newval) argument
44 CPU (h_pc) = newval;
58 m32rxf_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval) argument
60 CPU (h_gr[regno]) = newval;
74 m32rxf_h_cr_set (SIM_CPU *current_cpu, UINT regno, USI newval) argument
76 SET_H_CR (regno, newval);
90 m32rxf_h_accum_set (SIM_CPU *current_cpu, DI newval) argument
92 SET_H_ACCUM (newval);
106 m32rxf_h_accums_set (SIM_CPU *current_cpu, UINT regno, DI newval) argument
108 SET_H_ACCUMS (regno, newval);
122 m32rxf_h_cond_set(SIM_CPU *current_cpu, BI newval) argument
138 m32rxf_h_psw_set(SIM_CPU *current_cpu, UQI newval) argument
154 m32rxf_h_bpsw_set(SIM_CPU *current_cpu, UQI newval) argument
170 m32rxf_h_bbpsw_set(SIM_CPU *current_cpu, UQI newval) argument
186 m32rxf_h_lock_set(SIM_CPU *current_cpu, BI newval) argument
[all...]
H A Dcpu.c42 m32rbf_h_pc_set (SIM_CPU *current_cpu, USI newval) argument
44 CPU (h_pc) = newval;
58 m32rbf_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval) argument
60 CPU (h_gr[regno]) = newval;
74 m32rbf_h_cr_set (SIM_CPU *current_cpu, UINT regno, USI newval) argument
76 SET_H_CR (regno, newval);
90 m32rbf_h_accum_set (SIM_CPU *current_cpu, DI newval) argument
92 SET_H_ACCUM (newval);
106 m32rbf_h_cond_set (SIM_CPU *current_cpu, BI newval) argument
108 CPU (h_cond) = newval;
122 m32rbf_h_psw_set(SIM_CPU *current_cpu, UQI newval) argument
138 m32rbf_h_bpsw_set(SIM_CPU *current_cpu, UQI newval) argument
154 m32rbf_h_bbpsw_set(SIM_CPU *current_cpu, UQI newval) argument
170 m32rbf_h_lock_set(SIM_CPU *current_cpu, BI newval) argument
[all...]
H A Dm32r2.c84 m32r2f_h_cr_set_handler (SIM_CPU *current_cpu, UINT cr, USI newval)
91 int new_sm = (newval & 0x80) != 0;
92 CPU (h_bpsw) = (newval >> 8) & 0xff;
93 CPU (h_psw) = newval & 0xff;
94 SET_H_COND (newval & 1);
114 CPU (h_bbpsw) = newval & 0xff;
117 SET_H_COND (newval & 1);
121 CPU (h_gr[H_GR_SP]) = newval;
123 CPU (h_cr[H_CR_SPI]) = newval;
127 CPU (h_gr[H_GR_SP]) = newval;
83 m32r2f_h_cr_set_handler(SIM_CPU *current_cpu, UINT cr, USI newval) argument
155 m32r2f_h_psw_set_handler(SIM_CPU *current_cpu, UQI newval) argument
175 m32r2f_h_accum_set_handler(SIM_CPU *current_cpu, DI newval) argument
199 m32r2f_h_accums_set_handler(SIM_CPU *current_cpu, UINT regno, DI newval) argument
[all...]
H A Dm32rx.c84 m32rxf_h_cr_set_handler (SIM_CPU *current_cpu, UINT cr, USI newval)
91 int new_sm = (newval & 0x80) != 0;
92 CPU (h_bpsw) = (newval >> 8) & 0xff;
93 CPU (h_psw) = newval & 0xff;
94 SET_H_COND (newval & 1);
114 CPU (h_bbpsw) = newval & 0xff;
117 SET_H_COND (newval & 1);
121 CPU (h_gr[H_GR_SP]) = newval;
123 CPU (h_cr[H_CR_SPI]) = newval;
127 CPU (h_gr[H_GR_SP]) = newval;
83 m32rxf_h_cr_set_handler(SIM_CPU *current_cpu, UINT cr, USI newval) argument
155 m32rxf_h_psw_set_handler(SIM_CPU *current_cpu, UQI newval) argument
175 m32rxf_h_accum_set_handler(SIM_CPU *current_cpu, DI newval) argument
199 m32rxf_h_accums_set_handler(SIM_CPU *current_cpu, UINT regno, DI newval) argument
[all...]
H A Dm32r.c165 m32rbf_h_cr_set_handler (SIM_CPU *current_cpu, UINT cr, USI newval)
172 int new_sm = (newval & 0x80) != 0;
173 CPU (h_bpsw) = (newval >> 8) & 0xff;
174 CPU (h_psw) = newval & 0xff;
175 SET_H_COND (newval & 1);
195 CPU (h_bbpsw) = newval & 0xff;
198 SET_H_COND (newval & 1);
202 CPU (h_gr[H_GR_SP]) = newval;
204 CPU (h_cr[H_CR_SPI]) = newval;
208 CPU (h_gr[H_GR_SP]) = newval;
164 m32rbf_h_cr_set_handler(SIM_CPU *current_cpu, UINT cr, USI newval) argument
236 m32rbf_h_psw_set_handler(SIM_CPU *current_cpu, UQI newval) argument
265 m32rbf_h_accum_set_handler(SIM_CPU *current_cpu, DI newval) argument
[all...]
/netbsd-6-1-5-RELEASE/external/gpl3/gdb/dist/sim/iq2000/
H A Dcpu.c42 iq2000bf_h_pc_set (SIM_CPU *current_cpu, USI newval) argument
44 SET_H_PC (newval);
58 iq2000bf_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval) argument
60 SET_H_GR (regno, newval);
/netbsd-6-1-5-RELEASE/external/gpl3/gdb/dist/sim/frv/
H A Dcpu.c42 frvbf_h_reloc_ann_set (SIM_CPU *current_cpu, BI newval) argument
44 CPU (h_reloc_ann) = newval;
58 frvbf_h_pc_set (SIM_CPU *current_cpu, USI newval) argument
60 CPU (h_pc) = newval;
74 frvbf_h_psr_imple_set (SIM_CPU *current_cpu, UQI newval) argument
76 CPU (h_psr_imple) = newval;
90 frvbf_h_psr_ver_set (SIM_CPU *current_cpu, UQI newval) argument
92 CPU (h_psr_ver) = newval;
106 frvbf_h_psr_ice_set (SIM_CPU *current_cpu, BI newval) argument
108 CPU (h_psr_ice) = newval;
122 frvbf_h_psr_nem_set(SIM_CPU *current_cpu, BI newval) argument
138 frvbf_h_psr_cm_set(SIM_CPU *current_cpu, BI newval) argument
154 frvbf_h_psr_be_set(SIM_CPU *current_cpu, BI newval) argument
170 frvbf_h_psr_esr_set(SIM_CPU *current_cpu, BI newval) argument
186 frvbf_h_psr_ef_set(SIM_CPU *current_cpu, BI newval) argument
202 frvbf_h_psr_em_set(SIM_CPU *current_cpu, BI newval) argument
218 frvbf_h_psr_pil_set(SIM_CPU *current_cpu, UQI newval) argument
234 frvbf_h_psr_ps_set(SIM_CPU *current_cpu, BI newval) argument
250 frvbf_h_psr_et_set(SIM_CPU *current_cpu, BI newval) argument
266 frvbf_h_psr_s_set(SIM_CPU *current_cpu, BI newval) argument
282 frvbf_h_tbr_tba_set(SIM_CPU *current_cpu, USI newval) argument
298 frvbf_h_tbr_tt_set(SIM_CPU *current_cpu, UQI newval) argument
314 frvbf_h_bpsr_bs_set(SIM_CPU *current_cpu, BI newval) argument
330 frvbf_h_bpsr_bet_set(SIM_CPU *current_cpu, BI newval) argument
346 frvbf_h_gr_set(SIM_CPU *current_cpu, UINT regno, USI newval) argument
362 frvbf_h_gr_double_set(SIM_CPU *current_cpu, UINT regno, DI newval) argument
378 frvbf_h_gr_hi_set(SIM_CPU *current_cpu, UINT regno, UHI newval) argument
394 frvbf_h_gr_lo_set(SIM_CPU *current_cpu, UINT regno, UHI newval) argument
410 frvbf_h_fr_set(SIM_CPU *current_cpu, UINT regno, SF newval) argument
426 frvbf_h_fr_double_set(SIM_CPU *current_cpu, UINT regno, DF newval) argument
442 frvbf_h_fr_int_set(SIM_CPU *current_cpu, UINT regno, USI newval) argument
458 frvbf_h_fr_hi_set(SIM_CPU *current_cpu, UINT regno, UHI newval) argument
474 frvbf_h_fr_lo_set(SIM_CPU *current_cpu, UINT regno, UHI newval) argument
490 frvbf_h_fr_0_set(SIM_CPU *current_cpu, UINT regno, UHI newval) argument
506 frvbf_h_fr_1_set(SIM_CPU *current_cpu, UINT regno, UHI newval) argument
522 frvbf_h_fr_2_set(SIM_CPU *current_cpu, UINT regno, UHI newval) argument
538 frvbf_h_fr_3_set(SIM_CPU *current_cpu, UINT regno, UHI newval) argument
554 frvbf_h_cpr_set(SIM_CPU *current_cpu, UINT regno, SI newval) argument
570 frvbf_h_cpr_double_set(SIM_CPU *current_cpu, UINT regno, DI newval) argument
586 frvbf_h_spr_set(SIM_CPU *current_cpu, UINT regno, USI newval) argument
602 frvbf_h_accg_set(SIM_CPU *current_cpu, UINT regno, USI newval) argument
618 frvbf_h_acc40S_set(SIM_CPU *current_cpu, UINT regno, DI newval) argument
634 frvbf_h_acc40U_set(SIM_CPU *current_cpu, UINT regno, UDI newval) argument
650 frvbf_h_iacc0_set(SIM_CPU *current_cpu, UINT regno, DI newval) argument
666 frvbf_h_iccr_set(SIM_CPU *current_cpu, UINT regno, UQI newval) argument
682 frvbf_h_fccr_set(SIM_CPU *current_cpu, UINT regno, UQI newval) argument
698 frvbf_h_cccr_set(SIM_CPU *current_cpu, UINT regno, UQI newval) argument
[all...]
H A Dfrv.c142 frvbf_h_gr_set_handler (SIM_CPU *current_cpu, UINT gr, USI newval)
149 CPU (h_gr[gr]) = newval;
162 frvbf_h_fr_set_handler (SIM_CPU *current_cpu, UINT fr, SF newval)
165 CPU (h_fr[fr]) = newval;
286 frvbf_h_gr_double_set_handler (SIM_CPU *current_cpu, UINT gr, DI newval)
294 SET_H_GR (gr , (newval >> 32) & 0xffffffff);
295 SET_H_GR (gr + 1, (newval ) & 0xffffffff);
326 frvbf_h_fr_double_set_handler (SIM_CPU *current_cpu, UINT fr, DF newval)
336 value.as_df = newval;
364 frvbf_h_fr_int_set_handler (SIM_CPU *current_cpu, UINT fr, USI newval)
141 frvbf_h_gr_set_handler(SIM_CPU *current_cpu, UINT gr, USI newval) argument
160 frvbf_h_fr_set_handler(SIM_CPU *current_cpu, UINT fr, SF newval) argument
283 frvbf_h_gr_double_set_handler(SIM_CPU *current_cpu, UINT gr, DI newval) argument
322 frvbf_h_fr_double_set_handler(SIM_CPU *current_cpu, UINT fr, DF newval) argument
359 frvbf_h_fr_int_set_handler(SIM_CPU *current_cpu, UINT fr, USI newval) argument
386 frvbf_h_cpr_double_set_handler(SIM_CPU *current_cpu, UINT cpr, DI newval) argument
397 frvbf_h_gr_quad_set_handler(SIM_CPU *current_cpu, UINT gr, SI *newval) argument
412 frvbf_h_fr_quad_set_handler(SIM_CPU *current_cpu, UINT fr, SI *newval) argument
424 frvbf_h_cpr_quad_set_handler(SIM_CPU *current_cpu, UINT cpr, SI *newval) argument
467 frvbf_h_spr_set_handler(SIM_CPU *current_cpu, UINT spr, USI newval) argument
525 frvbf_h_gr_hi_set_handler(SIM_CPU *current_cpu, UINT gr, UHI newval) argument
538 frvbf_h_gr_lo_set_handler(SIM_CPU *current_cpu, UINT gr, UHI newval) argument
555 spr_tbr_set_handler(SIM_CPU *current_cpu, USI newval) argument
574 spr_bpsr_set_handler(SIM_CPU *current_cpu, USI newval) argument
604 spr_psr_set_handler(SIM_CPU *current_cpu, USI newval) argument
625 frvbf_h_psr_s_set_handler(SIM_CPU *current_cpu, BI newval) argument
654 spr_ccr_set_handler(SIM_CPU *current_cpu, USI newval) argument
713 spr_cccr_set_handler(SIM_CPU *current_cpu, USI newval) argument
741 spr_sr_set_handler(SIM_CPU *current_cpu, UINT spr, USI newval) argument
[all...]
/netbsd-6-1-5-RELEASE/external/gpl3/gdb/dist/sim/lm32/
H A Dcpu.c42 lm32bf_h_pc_set (SIM_CPU *current_cpu, USI newval) argument
44 CPU (h_pc) = newval;
58 lm32bf_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval) argument
60 CPU (h_gr[regno]) = newval;
74 lm32bf_h_csr_set (SIM_CPU *current_cpu, UINT regno, SI newval) argument
76 CPU (h_csr[regno]) = newval;
/netbsd-6-1-5-RELEASE/external/bsd/tmux/dist/compat/
H A Dsetenv.c28 char *newval; local
30 xasprintf(&newval, "%s=%s", name, value);
31 return (putenv(newval));
/netbsd-6-1-5-RELEASE/sys/arch/zaurus/dev/
H A Dlcdctlvar.h31 void lcdctl_brightness(int newval);
H A Dlcdctl.c192 lcdctl_set_brightness_internal(struct lcdctl_softc *sc, int newval) argument
201 if (newval > sc->sc_brightnesscurval) {
202 for (i = sc->sc_brightnesscurval + 1; i <= newval; i++) {
207 set_backlight(&sc->sc_backlighttbl[newval]);
209 sc->sc_brightnesscurval = newval;
213 lcdctl_set_brightness(struct lcdctl_softc *sc, int newval) argument
217 if (newval < 0)
218 newval = 0;
219 else if (newval > maxval)
220 newval
305 lcdctl_brightness(int newval) argument
[all...]
/netbsd-6-1-5-RELEASE/external/gpl3/gcc/dist/gcc/config/pa/
H A Dlinux-atomic.c52 __kernel_cmpxchg (int oldval, int newval, int *mem) argument
58 register int lws_new asm("r24") = newval;
119 unsigned int mask, shift, oldval, newval; \
127 newval = ((PFX_OP ((oldval & mask) >> shift) \
129 newval |= oldval & ~mask; \
130 failure = __kernel_cmpxchg (oldval, newval, wordptr); \
171 SUBWORD_SYNC_OP (add, , +, short, 2, newval)
172 SUBWORD_SYNC_OP (sub, , -, short, 2, newval)
173 SUBWORD_SYNC_OP (or, , |, short, 2, newval)
174 SUBWORD_SYNC_OP (and, , &, short, 2, newval)
186 __sync_val_compare_and_swap_4(int *ptr, int oldval, int newval) argument
239 __sync_bool_compare_and_swap_4(int *ptr, int oldval, int newval) argument
[all...]
/netbsd-6-1-5-RELEASE/external/gpl3/gcc/dist/gcc/config/arm/
H A Dlinux-atomic.c27 typedef int (__kernel_cmpxchg_t) (int oldval, int newval, int *ptr);
83 unsigned int mask, shift, oldval, newval; \
91 newval = ((PFX_OP (((oldval & mask) >> shift) \
93 newval |= oldval & ~mask; \
94 failure = __kernel_cmpxchg (oldval, newval, wordptr); \
135 SUBWORD_SYNC_OP (add, , +, unsigned short, 2, newval)
136 SUBWORD_SYNC_OP (sub, , -, unsigned short, 2, newval)
137 SUBWORD_SYNC_OP (or, , |, unsigned short, 2, newval)
138 SUBWORD_SYNC_OP (and, , &, unsigned short, 2, newval)
139 SUBWORD_SYNC_OP (xor, , ^, unsigned short, 2, newval)
150 __sync_val_compare_and_swap_4(int *ptr, int oldval, int newval) argument
203 __sync_bool_compare_and_swap_4(int *ptr, int oldval, int newval) argument
[all...]
/netbsd-6-1-5-RELEASE/sys/arch/hpcarm/dev/
H A Dj720pcic.c134 int newval, oldval, s; local
140 newval = 0;
143 newval = 2;
146 newval = 1;
157 newval = newval | (oldval & 0xc);
160 newval = (newval << 2) | (oldval & 3);
166 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACCGPIOA_DVR, newval);
/netbsd-6-1-5-RELEASE/sys/arch/ia64/include/
H A Datomic.h42 #define IA64_CMPXCHG(sz, sem, p, cmpval, newval, ret) \
47 : "r" (cmpval), "r" (newval), "m" (*p) \
54 ia64_cmpxchg_acq_32(volatile uint32_t* p, uint32_t cmpval, uint32_t newval) argument
57 IA64_CMPXCHG(4, acq, p, cmpval, newval, ret);
62 ia64_cmpxchg_rel_32(volatile uint32_t* p, uint32_t cmpval, uint32_t newval) argument
65 IA64_CMPXCHG(4, rel, p, cmpval, newval, ret);
70 ia64_cmpxchg_acq_64(volatile uint64_t* p, uint64_t cmpval, uint64_t newval) argument
73 IA64_CMPXCHG(8, acq, p, cmpval, newval, ret);
78 ia64_cmpxchg_rel_64(volatile uint64_t* p, uint64_t cmpval, uint64_t newval) argument
81 IA64_CMPXCHG(8, rel, p, cmpval, newval, re
284 atomic_cmpset_acq_32(volatile uint32_t* p, uint32_t cmpval, uint32_t newval) argument
290 atomic_cmpset_rel_32(volatile uint32_t* p, uint32_t cmpval, uint32_t newval) argument
301 atomic_cmpset_acq_64(volatile uint64_t* p, uint64_t cmpval, uint64_t newval) argument
307 atomic_cmpset_rel_64(volatile uint64_t* p, uint64_t cmpval, uint64_t newval) argument
[all...]
/netbsd-6-1-5-RELEASE/external/gpl3/gdb/dist/sim/common/
H A Dsim-cpu.c78 sim_pc_set (sim_cpu *cpu, sim_cia newval)
80 (* CPU_PC_STORE (cpu)) (cpu, newval);
77 sim_pc_set(sim_cpu *cpu, sim_cia newval) argument
H A Dcgen-engine.h230 #define SEM_BRANCH_VIA_CACHE(cpu, sc, newval, pcvar) \
232 npc = (newval); \
236 #define SEM_BRANCH_VIA_ADDR(cpu, sc, newval, pcvar) \
238 npc = (newval); \
268 #define SEM_BRANCH_VIA_CACHE(cpu, sc, newval, pcvar) \
270 (pcvar) = (newval); \
274 #define SEM_BRANCH_VIA_ADDR(cpu, sc, newval, pcvar) \
276 (pcvar) = (newval); \
295 #define SEM_BRANCH_VIA_CACHE(cpu, abuf, newval, pcvar) \
297 (pcvar) = (newval); \
[all...]
/netbsd-6-1-5-RELEASE/external/gpl3/gdb/dist/sim/testsuite/sim/cris/c/
H A Dsysctl1.c22 void *newval; member in struct:__sysctl_args
/netbsd-6-1-5-RELEASE/external/bsd/bind/dist/lib/dns/include/dns/
H A Dpeer.h138 dns_peer_setbogus(dns_peer_t *peer, isc_boolean_t newval);
144 dns_peer_setrequestixfr(dns_peer_t *peer, isc_boolean_t newval);
150 dns_peer_setprovideixfr(dns_peer_t *peer, isc_boolean_t newval);
156 dns_peer_setrequestnsid(dns_peer_t *peer, isc_boolean_t newval);
162 dns_peer_setsupportedns(dns_peer_t *peer, isc_boolean_t newval);
168 dns_peer_settransfers(dns_peer_t *peer, isc_uint32_t newval);
174 dns_peer_settransferformat(dns_peer_t *peer, dns_transfer_format_t newval);
/netbsd-6-1-5-RELEASE/external/gpl3/gcc/dist/libstdc++-v3/testsuite/util/
H A Dtestsuite_rvalref.h51 operator=(int newval) argument
54 val = newval;
126 operator=(int newval) argument
128 val = newval;

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