Searched refs:u32 (Results 1 - 25 of 3721) sorted by relevance

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/u-boot/arch/arm/include/asm/arch-lpc32xx/
H A Dmux.h14 u32 reserved1[10];
15 u32 p2_mux_set;
16 u32 p2_mux_clr;
17 u32 p2_mux_state;
18 u32 reserved2[51];
19 u32 p_mux_set;
20 u32 p_mux_clr;
21 u32 p_mux_state;
22 u32 reserved3;
23 u32 p3_mux_se
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H A Dgpio.h14 u32 p3_inp_state;
15 u32 p3_outp_set;
16 u32 p3_outp_clr;
17 u32 p3_outp_state;
19 u32 p2_p3_dir_set;
20 u32 p2_p3_dir_clr;
21 u32 p2_p3_dir_state;
23 u32 p2_inp_state;
24 u32 p2_outp_set;
25 u32 p2_outp_cl
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/u-boot/drivers/ram/k3-ddrss/am64/
H A Dlpddr4_ctl_regs.h22 volatile u32 DENALI_CTL_0;
23 volatile u32 DENALI_CTL_1;
24 volatile u32 DENALI_CTL_2;
25 volatile u32 DENALI_CTL_3;
26 volatile u32 DENALI_CTL_4;
27 volatile u32 DENALI_CTL_5;
28 volatile u32 DENALI_CTL_6;
29 volatile u32 DENALI_CTL_7;
30 volatile u32 DENALI_CTL_8;
31 volatile u32 DENALI_CTL_
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/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dnic301.h10 u32 remap; /* 0x0 */
12 u32 _pad_0x4_0x8[1];
13 u32 l4main;
14 u32 l4sp;
15 u32 l4mp; /* 0x10 */
16 u32 l4osc1;
17 u32 l4spim;
18 u32 stm;
19 u32 lwhps2fpgaregs; /* 0x20 */
20 u32 _pad_0x24_0x2
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/u-boot/drivers/ram/k3-ddrss/am62a/
H A Dlpddr4_ctl_regs.h24 volatile u32 DENALI_CTL_0;
25 volatile u32 DENALI_CTL_1;
26 volatile u32 DENALI_CTL_2;
27 volatile u32 DENALI_CTL_3;
28 volatile u32 DENALI_CTL_4;
29 volatile u32 DENALI_CTL_5;
30 volatile u32 DENALI_CTL_6;
31 volatile u32 DENALI_CTL_7;
32 volatile u32 DENALI_CTL_8;
33 volatile u32 DENALI_CTL_
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/u-boot/arch/arm/include/asm/arch-tegra124/
H A Dahb.h11 u32 reserved0; /* 00h */
12 u32 arbitration_disable; /* _ARBITRATION_DISABLE_0, 04h */
13 u32 arbitration_priority_ctrl; /* _ARBITRATION_PRIORITY_CTRL_0,08h */
14 u32 arbitration_usr_protect; /* _ARBITRATION_USR_PROTECT_0, 0ch */
15 u32 gizmo_ahb_mem; /* _GIZMO_AHB_MEM_0, 10h */
16 u32 gizmo_apb_dma; /* _GIZMO_APB_DMA_0, 14h */
17 u32 reserved6[2]; /* 18h, 1ch */
18 u32 gizmo_usb; /* _GIZMO_USB_0, 20h */
19 u32 gizmo_ahb_xbar_bridge; /* _GIZMO_AHB_XBAR_BRIDGE_0, 24h */
20 u32 gizmo_cpu_ahb_bridg
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H A Dgp_padctrl.h14 u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */
15 u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */
16 u32 reserved0[22]; /* 0x08 - 0x5C: */
17 u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */
18 u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
19 u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
20 u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */
21 u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
22 u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
23 u32 atcfg
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H A Dmc.h13 u32 reserved0[4]; /* offset 0x00 - 0x0C */
14 u32 mc_smmu_config; /* offset 0x10 */
15 u32 mc_smmu_tlb_config; /* offset 0x14 */
16 u32 mc_smmu_ptc_config; /* offset 0x18 */
17 u32 mc_smmu_ptb_asid; /* offset 0x1C */
18 u32 mc_smmu_ptb_data; /* offset 0x20 */
19 u32 reserved1[3]; /* offset 0x24 - 0x2C */
20 u32 mc_smmu_tlb_flush; /* offset 0x30 */
21 u32 mc_smmu_ptc_flush; /* offset 0x34 */
22 u32 reserved
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/u-boot/arch/arm/include/asm/arch-tegra210/
H A Dahb.h11 u32 reserved0; /* 00h */
12 u32 arbitration_disable; /* _ARBITRATION_DISABLE_0, 04h */
13 u32 arbitration_priority_ctrl; /* _ARBITRATION_PRIORITY_CTRL_0,08h */
14 u32 arbitration_usr_protect; /* _ARBITRATION_USR_PROTECT_0, 0ch */
15 u32 gizmo_ahb_mem; /* _GIZMO_AHB_MEM_0, 10h */
16 u32 gizmo_apb_dma; /* _GIZMO_APB_DMA_0, 14h */
17 u32 reserved6[2]; /* 18h, 1ch */
18 u32 gizmo_usb; /* _GIZMO_USB_0, 20h */
19 u32 gizmo_ahb_xbar_bridge; /* _GIZMO_AHB_XBAR_BRIDGE_0, 24h */
20 u32 gizmo_cpu_ahb_bridg
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H A Dgp_padctrl.h14 u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */
15 u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */
16 u32 reserved0[22]; /* 0x08 - 0x5C: */
17 u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */
18 u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
19 u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
20 u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */
21 u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
22 u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
23 u32 atcfg
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H A Dmc.h13 u32 reserved0[4]; /* offset 0x00 - 0x0C */
14 u32 mc_smmu_config; /* offset 0x10 */
15 u32 mc_smmu_tlb_config; /* offset 0x14 */
16 u32 mc_smmu_ptc_config; /* offset 0x18 */
17 u32 mc_smmu_ptb_asid; /* offset 0x1C */
18 u32 mc_smmu_ptb_data; /* offset 0x20 */
19 u32 reserved1[3]; /* offset 0x24 - 0x2C */
20 u32 mc_smmu_tlb_flush; /* offset 0x30 */
21 u32 mc_smmu_ptc_flush; /* offset 0x34 */
22 u32 reserved
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/u-boot/arch/arm/include/asm/arch-tegra20/
H A Dmc.h14 u32 reserved0[3]; /* offset 0x00 - 0x08 */
15 u32 mc_emem_cfg; /* offset 0x0C */
16 u32 mc_emem_adr_cfg; /* offset 0x10 */
17 u32 mc_emem_arb_cfg0; /* offset 0x14 */
18 u32 mc_emem_arb_cfg1; /* offset 0x18 */
19 u32 mc_emem_arb_cfg2; /* offset 0x1C */
20 u32 reserved1; /* offset 0x20 */
21 u32 mc_gart_cfg; /* offset 0x24 */
22 u32 mc_gart_entry_addr; /* offset 0x28 */
23 u32 mc_gart_entry_dat
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H A Demc.h16 u32 cfg; /* 0x00: EMC_CFG */
17 u32 reserved0[3]; /* 0x04 ~ 0x0C */
18 u32 adr_cfg; /* 0x10: EMC_ADR_CFG */
19 u32 adr_cfg1; /* 0x14: EMC_ADR_CFG_1 */
20 u32 reserved1[2]; /* 0x18 ~ 0x18 */
21 u32 refresh_ctrl; /* 0x20: EMC_REFCTRL */
22 u32 pin; /* 0x24: EMC_PIN */
23 u32 timing_ctrl; /* 0x28: EMC_TIMING_CONTROL */
24 u32 rc; /* 0x2C: EMC_RC */
25 u32 rf
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H A Dsdram_param.h29 u32 pllm_charge_pump_setup_control;
30 u32 pllm_loop_filter_setup_control;
31 u32 pllm_input_divider;
32 u32 pllm_feedback_divider;
33 u32 pllm_post_divider;
34 u32 pllm_stable_time;
35 u32 emc_clock_divider;
36 u32 emc_auto_cal_interval;
37 u32 emc_auto_cal_config;
38 u32 emc_auto_cal_wai
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H A Dgp_padctrl.h14 u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */
15 u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */
16 u32 reserved0[22]; /* 0x08 - 0x5C: */
17 u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */
18 u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
19 u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
20 u32 aocfg2; /* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */
21 u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
22 u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
23 u32 cdevcfg
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/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dpmu_rk3399.h11 u32 pmu_wakeup_cfg[5];
12 u32 pmu_pwrdn_con;
13 u32 pmu_pwrdn_st;
14 u32 pmu_pll_con;
15 u32 pmu_pwrmode_con;
16 u32 pmu_sft_con;
17 u32 pmu_int_con;
18 u32 pmu_int_st;
19 u32 pmu_gpio0_pos_int_con;
20 u32 pmu_gpio0_net_int_co
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H A Dgrf_rv1108.h9 u32 reserved[4];
10 u32 gpio1a_iomux;
11 u32 gpio1b_iomux;
12 u32 gpio1c_iomux;
13 u32 gpio1d_iomux;
14 u32 gpio2a_iomux;
15 u32 gpio2b_iomux;
16 u32 gpio2c_iomux;
17 u32 gpio2d_iomux;
18 u32 gpio3a_iomu
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H A Dsdram_rk3036.h9 u32 scfg;
10 u32 sctl;
11 u32 stat;
12 u32 intrstat;
13 u32 reserved0[12];
14 u32 mcmd;
15 u32 powctl;
16 u32 powstat;
17 u32 cmdtstat;
18 u32 cmdtstate
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/u-boot/arch/arm/mach-exynos/include/mach/
H A Dtmu.h24 u32 triminfo;
25 u32 rsvd1[4];
26 u32 triminfo_control;
27 u32 rsvd5[2];
28 u32 tmu_control;
29 u32 rsvd7;
30 u32 tmu_status;
31 u32 sampling_internal;
32 u32 counter_value0;
33 u32 counter_value
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/u-boot/drivers/ram/k3-ddrss/j721e/
H A Dlpddr4_ctl_regs.h22 volatile u32 DENALI_CTL_0;
23 volatile u32 DENALI_CTL_1;
24 volatile u32 DENALI_CTL_2;
25 volatile u32 DENALI_CTL_3;
26 volatile u32 DENALI_CTL_4;
27 volatile u32 DENALI_CTL_5;
28 volatile u32 DENALI_CTL_6;
29 volatile u32 DENALI_CTL_7;
30 volatile u32 DENALI_CTL_8;
31 volatile u32 DENALI_CTL_
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H A Dlpddr4_j721e_ctl_regs_rw_masks.h14 extern u32 g_lpddr4_ddr_controller_rw_mask[459];
15 extern u32 g_lpddr4_pi_rw_mask[300];
16 extern u32 g_lpddr4_data_slice_0_rw_mask[140];
17 extern u32 g_lpddr4_data_slice_1_rw_mask[140];
18 extern u32 g_lpddr4_data_slice_2_rw_mask[140];
19 extern u32 g_lpddr4_data_slice_3_rw_mask[140];
20 extern u32 g_lpddr4_address_slice_0_rw_mask[52];
21 extern u32 g_lpddr4_phy_core_rw_mask[143];
/u-boot/arch/arm/mach-at91/include/mach/
H A Dsama5_matrix.h13 u32 mcfg[16]; /* 0x00 ~ 0x3c: Master Configuration Register */
14 u32 scfg[16]; /* 0x40 ~ 0x7c: Slave Configuration Register */
15 u32 pras[16][2];/* 0x80 ~ 0xfc: Priority Register A/B */
16 u32 res1[20]; /* 0x100 ~ 0x14c */
17 u32 meier; /* 0x150: Master Error Interrupt Enable Register */
18 u32 meidr; /* 0x154: Master Error Interrupt Disable Register */
19 u32 meimr; /* 0x158: Master Error Interrupt Mask Register */
20 u32 mesr; /* 0x15c: Master Error Status Register */
21 u32 mear[16]; /* 0x160 ~ 0x19c: Master Error Address Register */
22 u32 res
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/u-boot/arch/arm/include/asm/arch-sunxi/
H A Ddram_sun8i_a23.h17 u32 clock;
18 u32 type;
19 u32 zq;
20 u32 odt_en;
22 u32 para1;
23 u32 para2;
24 u32 mr0;
25 u32 mr1;
26 u32 mr2;
27 u32 mr
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/u-boot/arch/arm/include/asm/arch-tegra30/
H A Dgp_padctrl.h13 u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */
14 u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */
15 u32 reserved0[22]; /* 0x08 - 0x5C: */
16 u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */
17 u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
18 u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
19 u32 aocfg2; /* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */
20 u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
21 u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
22 u32 atcfg
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/u-boot/arch/arm/include/asm/arch-tegra114/
H A Dgp_padctrl.h13 u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */
14 u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */
15 u32 reserved0[22]; /* 0x08 - 0x5C: */
16 u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */
17 u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
18 u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
19 u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */
20 u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
21 u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
22 u32 atcfg
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