Searched refs:rx_channel (Results 1 - 4 of 4) sorted by relevance

/u-boot/arch/arm/mach-tegra/
H A Divc.c30 * rx_channel.
54 * through the rx_channel pointer. This delineates ownership of the cache lines,
163 WRITE_ONCE(ivc->rx_channel->r_count,
164 READ_ONCE(ivc->rx_channel->r_count) + 1);
192 * asynchronous transition of rx_channel->state to ivc_state_ack is not
204 if (!tegra_ivc_channel_empty(ivc, ivc->rx_channel))
208 tegra_ivc_invalidate_counter(ivc, ivc->rx_channel, offset);
209 return tegra_ivc_channel_empty(ivc, ivc->rx_channel) ? -ENOMEM : 0;
251 tegra_ivc_invalidate_frame(ivc, ivc->rx_channel, ivc->r_pos);
252 *frame = tegra_ivc_frame_pointer(ivc, ivc->rx_channel, iv
[all...]
/u-boot/arch/arm/include/asm/arch-tegra/
H A Divc.h46 * rx_channel - Pointer to the shared memory region used to receive
49 struct tegra_ivc_channel_header *rx_channel; member in struct:tegra_ivc
56 * r_pos - The position in list of frames in rx_channel that we are
/u-boot/drivers/usb/musb-new/
H A Dmusb_host.c381 if (ep->rx_channel) {
382 dma->channel_release(ep->rx_channel);
383 ep->rx_channel = NULL;
713 dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel;
720 hw_ep->rx_channel = dma_channel;
876 hw_ep->rx_channel = dma_channel = NULL;
1401 dma = is_dma_capable() ? ep->rx_channel : NULL;
1454 dma = is_dma_capable() ? hw_ep->rx_channel : NULL;
1752 hw_ep->rx_channel = NULL;
2142 dma = is_in ? ep->rx_channel
[all...]
H A Dmusb_core.h256 struct dma_channel *rx_channel; member in struct:musb_hw_ep

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