Searched refs:rl_phase_val (Results 1 - 1 of 1) sorted by relevance
| /u-boot/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_leveling.c | 1730 int rl_adll_val, rl_phase_val, sdr_cycle_incr, rd_sample, rd_ready; local
1864 rl_phase_val = sdr_cycle_incr / MAX_RD_SAMPLES;
1866 ((rl_phase_val & RL_PH_SEL_MASK) << RL_PH_SEL_OFFS);
2039 rl_phase_val = i / MAX_RD_SAMPLES;
2040 rl_phase_val -= phase_delta;
2042 ("%s: final results: cs %d, subphy %d, read sample %d read ready %d, rl_phase_val %d, rl_adll_val %d\n",
2044 final_rd_ready, rl_phase_val, rl_adll_val));
2047 ((rl_phase_val & RL_PH_SEL_MASK) << RL_PH_SEL_OFFS);
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