/u-boot/arch/arm/mach-socfpga/ |
H A D | freeze_controller.c | 29 u32 reg_value; local 81 reg_value = readl(&freeze_controller_base->hioctrl); 85 reg_value 86 = (reg_value & ~reg_cfg_mask) 89 writel(reg_value, &freeze_controller_base->hioctrl); 95 reg_value = readl(&freeze_controller_base->hioctrl); 96 reg_value 97 = (reg_value & 100 writel(reg_value, &freeze_controller_base->hioctrl); 111 u32 reg_value; local [all...] |
/u-boot/drivers/ram/k3-ddrss/ |
H A D | cps_drv_lpddr4.h | 28 #define CPS_FLD_READ(fld, reg_value) (cps_fldread((u32)(CPS_FLD_MASK(fld)), \ 30 (u32)(reg_value))) 32 #define CPS_FLD_WRITE(fld, reg_value, value) (cps_fldwrite((u32)(CPS_FLD_MASK(fld)), \ 34 (u32)(reg_value), (u32)(value))) 36 #define CPS_FLD_SET(fld, reg_value) (cps_fldset((u32)(CPS_FLD_WIDTH(fld)), \ 39 (u32)(reg_value))) 42 #define CPS_FLD_CLEAR(reg, fld, reg_value) (cps_fldclear((u32)(CPS_FLD_WIDTH(fld)), \ 46 (u32)(reg_value))) 61 static inline u32 cps_fldread(u32 mask, u32 shift, u32 reg_value); 62 static inline u32 cps_fldread(u32 mask, u32 shift, u32 reg_value) argument 70 cps_fldwrite(u32 mask, u32 shift, u32 reg_value, u32 value) argument 79 cps_fldset(u32 width, u32 mask, u32 is_woclr, u32 reg_value) argument 91 cps_fldclear(u32 width, u32 mask, u32 is_woset, u32 is_woclr, u32 reg_value) argument [all...] |
/u-boot/drivers/ram/rockchip/ |
H A D | sdram_rk3399.c | 348 u32 reg_value; local 445 reg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq; 448 clrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8); 450 clrsetbits_le32(&denali_phy[914], 0xfff, reg_value); 452 clrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16); 454 clrsetbits_le32(&denali_phy[915], 0xfff, reg_value); 456 reg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac; 459 clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16); 480 reg_value = ((PHY_BOOSTP_EN << 4) | PHY_BOOSTN_EN); 482 clrsetbits_le32(&denali_phy[925], 0xff << 8, reg_value << 576 u32 reg_value; local 1901 u32 reg_value; local 1948 u32 reg_value; local 1995 u32 reg_value; local 2042 u32 reg_value; local 2091 u32 reg_value; local [all...] |
/u-boot/drivers/net/phy/ |
H A D | cortina.c | 280 fw_temp.reg_value = (simple_strtoul(reg_data, NULL, 0)) & 282 phy_write(phydev, 0x00, fw_temp.reg_addr, fw_temp.reg_value); 292 int reg_value; local 306 reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_BIST_STATUS); 307 if (reg_value & mseq_edc_bist_done) { 308 if (0 == (reg_value & mseq_edc_bist_fail)) 322 reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS); 323 if (reg_value) { 355 int reg_value; local 357 reg_value [all...] |
/u-boot/drivers/led/ |
H A D | led_cortina.c | 173 u32 reg_value, val; local 179 reg_value = 0; 180 reg_value |= LED_CLK_POLARITY; 188 reg_value |= (rate1 & LED_BLINK_RATE1_MASK) << 194 reg_value |= (rate2 & LED_BLINK_RATE2_MASK) << 197 cortina_led_write(plat->ctrl_regs, reg_value);
|
/u-boot/include/ |
H A D | cortina.h | 76 unsigned short reg_value; member in struct:cortina_reg_config
|
/u-boot/drivers/video/sunxi/ |
H A D | sunxi_de2.c | 40 u32 reg_value; local 43 reg_value = readl(SUNXI_SRAMC_BASE + 0x04); 44 reg_value &= ~(0x01 << 24); 45 writel(reg_value, SUNXI_SRAMC_BASE + 0x04);
|
/u-boot/drivers/usb/musb-new/ |
H A D | sunxi.c | 176 u32 reg_value; local 179 reg_value = readl(SUNXI_SRAMC_BASE + 0x04); 180 reg_value &= ~(0x03 << 0); 181 reg_value |= BIT(0); 182 writel(reg_value, SUNXI_SRAMC_BASE + 0x04);
|
/u-boot/drivers/phy/allwinner/ |
H A D | phy-sun4i-usb.c | 185 u32 bits, reg_value; local 198 reg_value = readl(usb_phy->pmu); 201 reg_value |= bits; 203 reg_value &= ~bits; 205 writel(reg_value, usb_phy->pmu);
|
/u-boot/drivers/ddr/marvell/axp/ |
H A D | ddr3_hw_training.h | 288 u32 reg_value; member in struct:dram_training_init 293 u32 reg_value; member in struct:dram_mv_init
|
H A D | ddr3_init.c | 796 ddr_mode->vals[j].reg_value); 894 ddr_mode->regs[j].reg_value);
|
/u-boot/drivers/net/ |
H A D | cortina_ni.c | 965 int ret, reg_value; local 994 ca_reg_read(®_value, (u64)priv->per_mdio_base_addr, 996 reg_value = reg_value | 0x00280000; 997 ca_reg_write(®_value, (u64)priv->per_mdio_base_addr,
|