Searched refs:reg_index (Results 1 - 3 of 3) sorted by relevance
/u-boot/arch/arm/include/asm/mach-imx/ |
H A D | mu_hal.h | 10 int mu_hal_sendmsg(ulong base, u32 reg_index, u32 msg); 11 int mu_hal_receivemsg(ulong base, u32 reg_index, u32 *msg);
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/u-boot/drivers/misc/imx_ele/ |
H A D | ele_mu.c | 36 int mu_hal_sendmsg(ulong base, u32 reg_index, u32 msg) argument 39 u32 mask = MU_SR_TE0_MASK << reg_index; 43 assert(reg_index < MU_TR_COUNT); 54 debug("tr[%d] 0x%x\n", reg_index, msg); 56 writel(msg, &mu_base->tr[reg_index]); 61 int mu_hal_receivemsg(ulong base, u32 reg_index, u32 *msg) argument 64 u32 mask = MU_SR_RF0_MASK << reg_index; 69 assert(reg_index < MU_RR_COUNT); 89 *msg = readl(&mu_base->rr[reg_index]); 91 debug("rr[%d] 0x%x\n", reg_index, *ms [all...] |
/u-boot/drivers/misc/imx8/ |
H A D | scu.c | 51 static int mu_hal_sendmsg(struct mu_type *base, u32 reg_index, u32 msg) argument 53 u32 mask = MU_SR_TE0_MASK >> reg_index; 57 assert(reg_index < MU_TR_COUNT); 66 writel(msg, &base->tr[reg_index]); 71 static int mu_hal_receivemsg(struct mu_type *base, u32 reg_index, u32 *msg) argument 73 u32 mask = MU_SR_RF0_MASK >> reg_index; 77 assert(reg_index < MU_TR_COUNT); 86 *msg = readl(&base->rr[reg_index]);
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