Searched refs:reg_addr (Results 1 - 25 of 63) sorted by relevance

123

/u-boot/arch/arm/include/asm/arch-imx8ulp/
H A Dupower.h12 int upower_pmic_i2c_write(u32 reg_addr, u32 reg_val);
13 int upower_pmic_i2c_read(u32 reg_addr, u32 *reg_val);
/u-boot/arch/arm/mach-socfpga/
H A Dsecure_reg_helper.c18 int socfpga_secure_convert_reg_id_to_addr(u32 id, phys_addr_t *reg_addr) argument
22 *reg_addr = socfpga_get_sysmgr_addr() + SYSMGR_SOC64_SDMMC;
25 *reg_addr = socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC0;
28 *reg_addr = socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC1;
31 *reg_addr = socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC2;
45 phys_addr_t reg_addr; local
46 ret = socfpga_secure_convert_reg_id_to_addr(id, &reg_addr);
50 args[0] = (u64)reg_addr;
65 phys_addr_t reg_addr; local
66 ret = socfpga_secure_convert_reg_id_to_addr(id, &reg_addr);
80 phys_addr_t reg_addr; local
[all...]
/u-boot/drivers/video/nexell/soc/
H A Ds5pxx18_soc_hdmi.c17 u32 *reg_addr; local
20 reg_addr = hdmi_base_addr + (offset / sizeof(u32));
21 regvalue = readl((u32 *)reg_addr);
29 u32 *reg_addr; local
31 reg_addr = hdmi_base_addr + (offset_new / sizeof(u32));
32 writel(regvalue, (u32 *)reg_addr);
/u-boot/drivers/video/exynos/
H A Dexynos_dp_lowlevel.h28 unsigned int reg_addr,
31 unsigned int reg_addr,
34 unsigned int reg_addr,
38 unsigned int reg_addr,
43 unsigned int reg_addr);
46 unsigned int reg_addr, unsigned int *data);
49 unsigned int reg_addr, unsigned int count,
H A Dexynos_dp_lowlevel.c476 unsigned int reg_addr,
486 reg = AUX_ADDR_7_0(reg_addr);
488 reg = AUX_ADDR_15_8(reg_addr);
490 reg = AUX_ADDR_19_16(reg_addr);
516 unsigned int reg_addr,
527 reg = AUX_ADDR_7_0(reg_addr);
529 reg = AUX_ADDR_15_8(reg_addr);
531 reg = AUX_ADDR_19_16(reg_addr);
555 unsigned int reg_addr,
581 reg = AUX_ADDR_7_0(reg_addr
475 exynos_dp_write_byte_to_dpcd(struct exynos_dp *dp_regs, unsigned int reg_addr, unsigned char data) argument
515 exynos_dp_read_byte_from_dpcd(struct exynos_dp *dp_regs, unsigned int reg_addr, unsigned char *data) argument
554 exynos_dp_write_bytes_to_dpcd(struct exynos_dp *dp_regs, unsigned int reg_addr, unsigned int count, unsigned char data[]) argument
620 exynos_dp_read_bytes_from_dpcd(struct exynos_dp *dp_regs, unsigned int reg_addr, unsigned int count, unsigned char data[]) argument
687 exynos_dp_select_i2c_device(struct exynos_dp *dp_regs, unsigned int device_addr, unsigned int reg_addr) argument
719 exynos_dp_read_byte_from_i2c(struct exynos_dp *dp_regs, unsigned int device_addr, unsigned int reg_addr, unsigned int *data) argument
762 exynos_dp_read_bytes_from_i2c(struct exynos_dp *dp_regs, unsigned int device_addr, unsigned int reg_addr, unsigned int count, unsigned char edid[]) argument
[all...]
/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training_ip_flow.h59 u32 reg_addr; member in struct:mv_ddr_mr_data
74 u32 if_id, u32 reg_addr, u32 data_value, u32 mask);
79 u32 if_id, u32 reg_addr, u32 *data, u32 mask);
84 u32 reg_addr, u32 data_value, u32 reg_mask);
86 u32 phy_id, enum hws_ddr_phy phy_type, u32 reg_addr,
90 enum hws_ddr_phy e_phy_type, u32 reg_addr,
96 int ddr3_tip_ext_read(u32 dev_num, u32 if_id, u32 reg_addr,
98 int ddr3_tip_ext_write(u32 dev_num, u32 if_id, u32 reg_addr,
123 u32 reg_addr, u32 mask);
126 u32 reg_addr);
[all...]
H A Dddr3_training_pbs.c49 u32 reg_addr = 0; local
72 reg_addr = (pbs_mode == PBS_RX_MODE) ?
75 ddr3_tip_read_adll_value(dev_num, nominal_adll, reg_addr, MASK_ALL_BITS);
186 reg_addr = (pbs_mode == PBS_RX_MODE) ?
192 reg_addr, 0x1f));
193 reg_addr = (pbs_mode == PBS_RX_MODE) ?
199 reg_addr, 0x1f));
246 reg_addr = (pbs_mode == PBS_RX_MODE) ?
254 DDR_PHY_DATA, reg_addr,
256 reg_addr
943 u32 reg_addr = (pbs_mode == PBS_RX_MODE) ? local
993 u32 reg_addr = (pbs_mode == PBS_RX_MODE) ? local
[all...]
H A Dddr3_training_ip_prv_if.h42 u32 reg_addr, u32 data, u32 mask);
45 u32 reg_addr, u32 *data, u32 mask);
49 enum hws_ddr_phy phy_type, u32 reg_addr, u32 data);
52 u32 phy_id, enum hws_ddr_phy phy_type, u32 reg_addr, u32 *data);
102 u32 reg_addr, u32 *data);
105 u32 reg_addr, u32 data,
H A Dddr3_training_hw_algo.c164 u32 reg_addr = 0xa8; local
203 DDR_PHY_DATA, reg_addr, &val));
207 pup, DDR_PHY_DATA, reg_addr,
377 DDR_PHY_DATA, reg_addr,
385 DDR_PHY_DATA, reg_addr,
492 DDR_PHY_DATA, reg_addr,
500 DDR_PHY_DATA, reg_addr,
535 DDR_PHY_DATA, reg_addr,
543 DDR_PHY_DATA, reg_addr,
565 DDR_PHY_DATA, reg_addr,
[all...]
/u-boot/drivers/net/octeon/
H A Docteon_mdio.c57 int dev_addr, int reg_addr)
64 dev, dev->name, p->bus_id, phy_addr, dev_addr, reg_addr);
68 reg_addr);
70 value = cvmx_mdio_read(p->bus_id & 0xff, phy_addr, reg_addr);
78 int dev_addr, int reg_addr, u16 value)
84 __func__, dev, dev->name, p->bus_id, phy_addr, dev_addr, reg_addr,
90 reg_addr, value);
93 return cvmx_mdio_write(p->bus_id & 0xff, phy_addr, reg_addr, value);
99 * @param reg_addr MDIO base register address
103 int octeon_mdio_reg_addr_to_bus(u64 reg_addr) argument
56 octeon_mdio_read(struct udevice *mdio_dev, int phy_addr, int dev_addr, int reg_addr) argument
77 octeon_mdio_write(struct udevice *mdio_dev, int phy_addr, int dev_addr, int reg_addr, u16 value) argument
[all...]
/u-boot/arch/arm/mach-mvebu/serdes/a38x/
H A Dseq_exec.c33 u32 unit_base_reg, unit_offset, data, mask, reg_data, reg_addr; local
49 reg_addr = unit_base_reg + unit_offset * serdes_num;
52 printf("Write: 0x%x: 0x%x (mask 0x%x) - ", reg_addr, data, mask);
55 reg_data = reg_read(reg_addr);
61 reg_write(reg_addr, reg_data);
88 u32 reg_addr, reg_data; local
106 reg_addr = unit_base_reg + unit_offset * serdes_num;
110 printf("Poll: 0x%x: 0x%x (mask 0x%x)\n", reg_addr, data, mask);
114 reg_data = reg_read(reg_addr) & mask;
/u-boot/arch/arm/include/asm/arch-sunxi/
H A Drsb.h50 int rsb_write(const u16 runtime_device_addr, const u8 reg_addr, u8 data);
51 int rsb_read(const u16 runtime_device_addr, const u8 reg_addr, u8 *data);
/u-boot/drivers/net/octeontx2/
H A Dcgx.c85 void *reg_addr; local
88 reg_addr = lmac->cgx->reg_base +
90 writeq(dmac_cam0.u, reg_addr);
91 debug("%s: reg %p dmac_cam0 %llx\n", __func__, reg_addr, dmac_cam0.u);
97 reg_addr = lmac->cgx->reg_base +
99 writeq(dmac_ctl0.u, reg_addr);
100 debug("%s: reg %p dmac_ctl0 %llx\n", __func__, reg_addr, dmac_ctl0.u);
108 void *reg_addr; local
119 reg_addr = lmac->cgx->reg_base +
121 writeq(dmac_cam0.u, reg_addr);
[all...]
/u-boot/drivers/net/pfe_eth/
H A Dpfe_mdio.c20 int reg_addr)
31 reg_data = (EMAC_MII_DATA_TA | phy | devadr | reg_addr);
54 int reg_addr)
64 reg = ((reg_addr & EMAC_MII_DATA_RA_MASK) <<
67 pfe_write_addr(bus, phy_addr, dev_addr, reg_addr);
103 phy_addr, reg_addr, val);
109 int reg_addr, u16 data)
118 reg = ((reg_addr & EMAC_MII_DATA_RA_MASK) <<
121 pfe_write_addr(bus, phy_addr, dev_addr, reg_addr);
153 reg_addr, dat
19 pfe_write_addr(struct mii_dev *bus, int phy_addr, int dev_addr, int reg_addr) argument
53 pfe_phy_read(struct mii_dev *bus, int phy_addr, int dev_addr, int reg_addr) argument
108 pfe_phy_write(struct mii_dev *bus, int phy_addr, int dev_addr, int reg_addr, u16 data) argument
[all...]
/u-boot/arch/arm/mach-imx/imx8ulp/upower/
H A Dupower_hal.c76 int upower_pmic_i2c_write(u32 reg_addr, u32 reg_val) argument
81 ret = upwr_xcp_i2c_access(0x32, 1, 1, reg_addr, reg_val, NULL);
94 debug("PMIC write reg[0x%x], val[0x%x]\n", reg_addr, reg_val);
99 int upower_pmic_i2c_read(u32 reg_addr, u32 *reg_val) argument
107 ret = upwr_xcp_i2c_access(0x32, -1, 1, reg_addr, 0, NULL);
122 debug("PMIC read reg[0x%x], val[0x%x]\n", reg_addr, *reg_val);
/u-boot/arch/arm/mach-omap2/
H A Dvc.c91 * @reg_addr: I2C register address(8 bit) address in PMIC
94 int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data) argument
104 reg_addr &= PRM_VC_VAL_BYPASS_REGADDR_MASK;
109 reg_addr << PRM_VC_VAL_BYPASS_REGADDR_SHIFT |
/u-boot/drivers/gpio/
H A Dmcp230xx_gpio.c42 static int mcp230xx_read_spi(struct udevice *dev, uint reg_addr) argument
64 ret = dm_spi_xfer(dev, 8, &reg_addr, NULL, 0);
84 int reg_addr = (reg << shift) | bank; local
91 ret = dm_i2c_reg_read(dev, reg_addr);
96 ret = mcp230xx_read_spi(dev, reg_addr);
108 static int mcp230xx_clrset_spi(struct udevice *dev, uint reg_addr, uint clr, uint set) argument
117 ret = mcp230xx_read_spi(dev, reg_addr);
138 ret = dm_spi_xfer(dev, 8, &reg_addr, NULL, 0);
156 int reg_addr = (reg << shift) | bank; local
162 return dm_i2c_reg_clrset(dev, reg_addr, mas
[all...]
/u-boot/drivers/i2c/
H A Dsun8i_rsb.c62 u8 reg_addr, u8 *data)
67 writel(reg_addr, &base->addr);
80 u8 reg_addr, u8 data)
83 writel(reg_addr, &base->addr);
138 int rsb_read(const u16 runtime_addr, const u8 reg_addr, u8 *data) argument
142 return sun8i_rsb_read(base, runtime_addr, reg_addr, data);
145 int rsb_write(const u16 runtime_addr, const u8 reg_addr, u8 data) argument
149 return sun8i_rsb_write(base, runtime_addr, reg_addr, data);
61 sun8i_rsb_read(struct sunxi_rsb_reg *base, u16 runtime_addr, u8 reg_addr, u8 *data) argument
79 sun8i_rsb_write(struct sunxi_rsb_reg *base, u16 runtime_addr, u8 reg_addr, u8 data) argument
/u-boot/drivers/video/bridge/
H A Danx6345.c25 unsigned char reg_addr, unsigned char value)
33 buf[0] = reg_addr;
40 __func__, reg_addr, value, ret);
48 unsigned char reg_addr, unsigned char *value)
56 addr = reg_addr;
66 __func__, (int)reg_addr, value, ret);
74 static int anx6345_write_r0(struct udevice *dev, unsigned char reg_addr, argument
79 return anx6345_write(dev, chip->chip_addr, reg_addr, value);
82 static int anx6345_read_r0(struct udevice *dev, unsigned char reg_addr, argument
87 return anx6345_read(dev, chip->chip_addr, reg_addr, valu
24 anx6345_write(struct udevice *dev, unsigned int addr_off, unsigned char reg_addr, unsigned char value) argument
47 anx6345_read(struct udevice *dev, unsigned int addr_off, unsigned char reg_addr, unsigned char *value) argument
90 anx6345_write_r1(struct udevice *dev, unsigned char reg_addr, unsigned char value) argument
98 anx6345_read_r1(struct udevice *dev, unsigned char reg_addr, unsigned char *value) argument
[all...]
H A Dps862x.c34 * @param reg_addr register address to write
39 unsigned char reg_addr, unsigned char value)
48 buf[0] = reg_addr;
55 __func__, reg_addr, value, ret);
38 ps8622_write(struct udevice *dev, unsigned addr_off, unsigned char reg_addr, unsigned char value) argument
/u-boot/drivers/bootcount/
H A Dbootcount_syscon.c26 * @reg_addr: register address used to store the bootcount value
36 fdt_addr_t reg_addr; member in struct:bootcount_syscon_priv
62 return regmap_update_bits(priv->regmap, priv->reg_addr, priv->reg_mask,
72 ret = regmap_read(priv->regmap, priv->reg_addr, &regval);
104 priv->reg_addr = dev_read_addr_size_name(dev, "syscon_reg", &reg_size);
105 if (priv->reg_addr == FDT_ADDR_T_NONE) {
/u-boot/cmd/
H A Dpci.c70 u32 reg_addr; local
91 reg_addr = PCI_BASE_ADDRESS_0;
93 dm_pci_read_config32(dev, reg_addr, &base_low);
94 dm_pci_write_config32(dev, reg_addr, 0xffffffff);
95 dm_pci_read_config32(dev, reg_addr, &size_low);
96 dm_pci_write_config32(dev, reg_addr, base_low);
97 reg_addr += 4;
109 dm_pci_read_config32(dev, reg_addr, &base_high);
110 dm_pci_write_config32(dev, reg_addr, 0xffffffff);
111 dm_pci_read_config32(dev, reg_addr,
[all...]
/u-boot/drivers/misc/
H A Dp2sb-uclass.c38 uintptr_t reg_addr; local
41 reg_addr = upriv->mmio_base;
42 reg_addr += pplat->pid << PCR_PORTID_SHIFT;
43 reg_addr += offset;
45 return map_sysmem(reg_addr, 4);
/u-boot/drivers/net/phy/
H A Dcortina.c134 char reg_addr[0x50] = {0}; local
275 memcpy(reg_addr, line_temp, i);
277 strim(reg_addr);
279 fw_temp.reg_addr = (simple_strtoul(reg_addr, NULL, 0)) & 0xffff;
282 phy_write(phydev, 0x00, fw_temp.reg_addr, fw_temp.reg_value);
/u-boot/include/
H A Dcortina.h75 unsigned short reg_addr; member in struct:cortina_reg_config

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