Searched refs:ram_size (Results 1 - 25 of 349) sorted by relevance

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/u-boot/board/freescale/ls1028a/
H A Dddr.c15 gd->ram_size = tfa_get_dram_size();
17 if (!gd->ram_size)
18 gd->ram_size = fsl_ddr_sdram_size();
/u-boot/board/freescale/lx2160a/
H A Dddr.c15 gd->ram_size = tfa_get_dram_size();
17 if (!gd->ram_size)
18 gd->ram_size = fsl_ddr_sdram_size();
/u-boot/board/freescale/ls1046afrwy/
H A Dddr.c14 gd->ram_size = tfa_get_dram_size();
16 if (!gd->ram_size)
17 gd->ram_size = fsl_ddr_sdram_size();
/u-boot/board/nuvoton/poleg_evb/
H A Dpoleg_evb.c30 gd->ram_size = 0x08000000; /* 128 MB. */
33 gd->ram_size = 0x10000000; /* 256 MB. */
36 gd->ram_size = 0x20000000; /* 512 MB. */
39 gd->ram_size = 0x40000000; /* 1024 MB. */
42 gd->ram_size = 0x80000000; /* 2048 MB. */
58 if (gd->ram_size > 0) {
59 sprintf(value, "%ldM", (gd->ram_size / 0x100000));
/u-boot/board/imgtec/boston/
H A Ddt.c17 mem_size[0] = min_t(u64, 256llu << 20, gd->ram_size);
20 if (gd->ram_size > mem_size[0]) {
22 mem_size[1] = gd->ram_size - mem_size[0];
/u-boot/board/solidrun/common/
H A Dtlv_data.h12 unsigned int ram_size; member in struct:tlv_data
/u-boot/board/imgtec/xilfpga/
H A Dxilfpga.c22 gd->ram_size = CFG_SYS_SDRAM_SIZE; /* in bytes */
/u-boot/board/hpe/gxp/
H A Dgxp_board.c32 gd->ram_size = SZ_128M + SZ_64M + SZ_32M + SZ_16M + SZ_8M;
35 gd->ram_size = SZ_256M + SZ_128M + SZ_64M + SZ_32M + SZ_16M;
41 gd->ram_size = SZ_128M + SZ_64M;
44 gd->ram_size = SZ_256M + SZ_128M;
51 gd->ram_size = SZ_128M + SZ_64M + SZ_32M;
54 gd->ram_size = SZ_256M + SZ_128M + SZ_64M;
61 gd->ram_size = SZ_256M + SZ_128M + SZ_32M + SZ_16M + SZ_2M;
64 gd->ram_size = SZ_256M + SZ_64M;
69 gd->ram_size = SZ_256M + SZ_128M;
/u-boot/arch/x86/cpu/ivybridge/
H A Dsdram_nop.c14 gd->ram_size = 1ULL << 31;
16 gd->bd->bi_dram[0].size = gd->ram_size;
/u-boot/board/nuvoton/arbel_evb/
H A Darbel_evb.c33 if (gd->ram_size > DRAM_2GB_SIZE)
36 return gd->ram_size;
49 gd->ram_size = readl(&gcr->scrpad_c);
51 if (gd->ram_size == 0)
52 gd->ram_size = readl(&gcr->scrpad_b);
54 gd->ram_size *= 0x100000ULL;
56 debug("ram_size: %llx ", gd->ram_size);
66 switch (gd->ram_size) {
73 gd->bd->bi_dram[0].size = gd->ram_size;
[all...]
/u-boot/arch/mips/mach-ath79/
H A Ddram.c17 gd->ram_size = get_ram_size((void *)KSEG1, SZ_256M);
/u-boot/board/bticino/mamoj/
H A Dmamoj.c25 gd->ram_size = imx_ddr_size();
/u-boot/board/freescale/mx6memcal/
H A Dmx6memcal.c30 gd->ram_size = imx_ddr_size();
/u-boot/common/init/
H A Dhandoff.c19 ho->ram_size = gd->ram_size;
29 gd->ram_size = ho->ram_size;
/u-boot/test/lib/
H A Dlmb.c22 phys_addr_t ram_base, phys_size_t ram_size,
28 if (ram_size) {
31 ut_asserteq(lmb->memory.region[0].size, ram_size);
50 #define ASSERT_LMB(lmb, ram_base, ram_size, num_reserved, base1, size1, \
52 ut_assert(!check_lmb(uts, lmb, ram_base, ram_size, \
61 const phys_size_t ram_size, const phys_addr_t ram0,
65 const phys_addr_t ram_end = ram + ram_size;
86 ret = lmb_add(&lmb, ram, ram_size);
94 ut_asserteq(lmb.memory.region[1].size, ram_size);
98 ut_asserteq(lmb.memory.region[0].size, ram_size);
21 check_lmb(struct unit_test_state *uts, struct lmb *lmb, phys_addr_t ram_base, phys_size_t ram_size, unsigned long num_reserved, phys_addr_t base1, phys_size_t size1, phys_addr_t base2, phys_size_t size2, phys_addr_t base3, phys_size_t size3) argument
60 test_multi_alloc(struct unit_test_state *uts, const phys_addr_t ram, const phys_size_t ram_size, const phys_addr_t ram0, const phys_size_t ram0_size, const phys_addr_t alloc_64k_addr) argument
229 const phys_size_t ram_size = 0x20000000; local
296 const phys_size_t ram_size = 0x20000000; local
388 const phys_size_t ram_size = 0x20000000; local
428 const phys_size_t ram_size = 0x20000000; local
478 const phys_size_t ram_size = 0x20000000; local
605 const phys_size_t ram_size = 0x20000000; local
680 const phys_size_t ram_size = ((0xFFFFFFFF >> CONFIG_LMB_MAX_REGIONS) local
744 const phys_size_t ram_size = 0x20000000; local
[all...]
/u-boot/common/
H A Dmemsize.c121 phys_size_t ram_size = gd->ram_size; local
126 * It is required that ram_base + ram_size must be representable by
131 if (gd->ram_base + ram_size < gd->ram_base)
132 ram_size = ((phys_size_t)~0xfffULL) - gd->ram_base;
136 return ram_size;
139 return ((ram_size > CFG_MAX_MEM_MAPPED) ?
140 CFG_MAX_MEM_MAPPED : ram_size);
/u-boot/arch/arm/mach-mediatek/mt7623/
H A Dinit.c33 gd->ram_size = 0;
36 gd->ram_size += preloader_param->dram_rank_size[i];
38 gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE,
/u-boot/arch/arm/mach-mvebu/armada8k/
H A Ddram.c42 if (gd->ram_size <= max_bank0_size) {
43 gd->bd->bi_dram[0].size = gd->ram_size;
50 gd->bd->bi_dram[1].size = gd->ram_size - max_bank0_size;
/u-boot/arch/x86/cpu/coreboot/
H A Dsdram.c67 phys_size_t ram_size = 0; local
73 if (memrange->type == CB_MEM_RAM && end > ram_size)
74 ram_size += memrange->size;
77 gd->ram_size = ram_size;
78 if (ram_size == 0)
/u-boot/drivers/ddr/altera/
H A Dsdram_agilex.c97 (phys_size_t *)&gd->ram_size, &bd);
103 if (gd->ram_size != hw_size) {
105 gd->ram_size >> 20);
110 if (gd->ram_size > hw_size) {
116 printf("DDR: %lld MiB\n", gd->ram_size >> 20);
120 FW_MPU_DDR_SCR_WRITEL(gd->ram_size - 1,
125 FW_MPU_DDR_SCR_WRITEL(gd->ram_size - 1,
167 priv->info.size = gd->ram_size;
/u-boot/arch/arm/mach-imx/mx5/
H A Dmx53_dram.c31 gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
32 gd->ram_size += get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
/u-boot/board/freescale/ls1012afrdm/
H A Dls1012afrdm.c91 gd->ram_size = tfa_get_dram_size();
93 if (!gd->ram_size) {
98 gd->ram_size = SYS_SDRAM_SIZE_1024;
100 gd->ram_size = SYS_SDRAM_SIZE_512;
102 gd->ram_size = CFG_SYS_SDRAM_SIZE;
134 gd->ram_size = SYS_SDRAM_SIZE_1024;
136 gd->ram_size = SYS_SDRAM_SIZE_512;
139 gd->ram_size = CFG_SYS_SDRAM_SIZE;
/u-boot/arch/mips/mach-octeon/
H A Ddram.c36 gd->ram_size = ram.size;
43 gd->ram_size = (4 << 20);
44 gd->bd->bi_dram[0].size = gd->ram_size;
84 return CFG_SYS_SDRAM_BASE + min(gd->ram_size,
/u-boot/arch/sandbox/cpu/
H A Dcache.c21 (void *)(state->ram_buf + state->ram_size));
/u-boot/board/sysam/stmark2/
H A Dstmark2.c40 gd->ram_size = dramsize;

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